Veryl

Announcing Veryl 0.20.1

2026-06-01T00:00:00+00:00

The Veryl team has published a new release of Veryl, 0.20.1. Veryl is a new hardware description language as an alternate to SystemVerilog.</p>

If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>

$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
New Language Features</h1>
Enum member import #2599</a>
</h2>
Enum members can now be imported via import</code>, so they can be referenced without
the enclosing enum's namespace prefix.
This is particularly useful when an enum is used heavily inside a single scope.</p>
package </span>PackageA {
</span>    </span>enum </span>EnumA: </span>logic</span><3> {
</span>        A,
</span>        B,
</span>        C,
</span>    }
</span>}
</span>
</span>module </span>ModuleA (
</span>    i_a: </span>input  </span>PackageA::EnumA,
</span>    o_d: </span>output logic</span>         ,
</span>) {
</span>    </span>import </span>PackageA::EnumA::*;
</span>
</span>    </span>//</span> Members can be referenced directly after `import`.
</span>    </span>assign </span>o_d = </span>inside </span>i_a {A, B, C};
</span>}
</span></code></pre>
New Tool Features</h1>
Combinational loop detection #2610</a>
</h2>
The analyzer now reports combinational loops at compile time, including loops
that traverse function calls and submodule instances.
Catching these statically avoids relying on the downstream simulator or synthesis
tool to discover the cycle.</p>
module </span>ModuleA (
</span>    a: </span>input  logic</span><8>,
</span>    b: </span>output logic</span><8>,
</span>) {
</span>    </span>var </span>c: </span>logic</span><8>;
</span>    </span>assign </span>b = c;
</span>    </span>assign </span>c = b;   </span>//</span> error: combinational loop detected
</span>}
</span></code></pre>
Wadler/Lindig based formatter #2614</a>
</h2>
The formatter has been rewritten on top of a Wadler/Lindig style pretty printer.
Line breaks are now decided by the target line width rather than purely by syntax,
so long expressions wrap into a readable shape instead of overflowing on a single
line.
The target width is configurable via format.max_width</code> in Veryl.toml</code>
(default: 120).</p>
//</span> before
</span>let </span>a: </span>logic</span><8> = aaaaaaaaaaaa + bbbbbbbbbbbb + cccccccccccc + dddddddddddd + eeeeeeeeeeee;
</span>
</span>//</span> after
</span>let </span>a: </span>logic</span><8> =
</span>    aaaaaaaaaaaa + bbbbbbbbbbbb + cccccccccccc + dddddddddddd
</span>    + eeeeeeeeeeee;
</span></code></pre>
In addition, several long-standing formatter bugs around case</code> expressions and
related constructs have been fixed as part of the rewrite.</p>
C compiler backend for the native simulator #2662</a>
</h2>
The native simulator gains a new cc</code> backend that emits C code and compiles it
with a system C compiler in the background, producing a more heavily optimized
binary than the existing Cranelift JIT path.
The simulation starts immediately on the Cranelift output and then transparently
switches over to the C-compiled binary once it is ready, combining low startup
latency with high steady-state throughput.</p>
$ veryl test --backend cc
</span></code></pre>
The backend used during a run can be selected via --backend {interpret,cranelift,cc}</code>.
If no C compiler is available, the backend falls back to Cranelift automatically.
See the previous post</a> for
performance numbers from this combined backend setup.</p>
--define</code> support for veryl test</code> #2597</a>
</h2>
veryl test</code> now accepts --define</code> on the command line, and test.defines</code> in
Veryl.toml</code>, so testbenches can be parameterized via macros in the same way as
veryl build</code>.</p>
#</span> Veryl.toml
</span>[test]
</span>defines </span>= [</span>"</span>SIM_FAST</span>"</span>]
</span></code></pre>
$ veryl test --define EXTRA_TRACE
</span></code></pre>
Gitoxide as the default Git backend #2640</a>
</h2>
The metadata layer now uses gitoxide</code></a>
by default for resolving Git dependencies, instead of shelling out to the system
git</code> command.
This removes the hard runtime requirement on an external git</code> binary — useful
in minimal container images and other environments where git</code> is not preinstalled.
If gitoxide</code> cannot handle a particular repository, Veryl transparently falls
back to the system git</code> command when it is available.</p>
The backend can be selected explicitly with the VERYL_GIT_BACKEND</code> environment
variable (auto</code>, gitoxide</code>, or command</code>).</p>
Other Changes</h1>
Check out everything that changed in Release v0.20.1</a>.</p>



Veryl Simulator: Performance Comparison with Verilator
2026-05-26T00:00:00+00:00
We have been working on a native Veryl simulator built on the new IR-based analyzer
introduced earlier this year. This post shares early performance numbers
comparing it against Verilator</a>, the de facto
standard open source SystemVerilog simulator.</p>
Approach</h2>
The Veryl simulator combines two execution backends:</p>

A Cranelift</a>-based backend</strong> that trades
optimization quality for compile speed, so the first run starts with little
upfront cost.</li>
A GCC-based backend</strong> that runs in the background to produce a more
heavily optimized binary. Once the optimized binary is ready, the running
simulation switches over to it dynamically.</li>
</ul>
In practice the simulation starts running almost immediately on the Cranelift
output, and then speeds up mid-run once GCC has finished compiling.</p>
Benchmark</h2>
We ran a Linux boot (about 30M simulated cycles) on
Heliodor</a>, an Out-of-Order RISC-V core
written in Veryl, with 1, 2, and 4 core configurations.</p>

Veryl: latest nightly (2026-05-26)</li>
Verilator: v5.040</li>
</ul>
The Veryl simulator also supports 4-state simulation. We used 2-state mode for
this benchmark because this version of Verilator is 2-state only.</p>
For each configuration we measured both the first run</em> (no cached artifacts) and
the cached run</em> (re-running after the optimized binary has been built), on two
machines representing different CPU generations.</p>
Intel Xeon Gold 6434 (Sapphire Rapids, 2023)</strong></p>

AMD Ryzen Threadripper 1950X (Zen 1, 2017)</strong></p>

Observations</h2>

On the first run</strong>, Cranelift's fast compilation lets Veryl start executing
noticeably sooner than Verilator, which spends a significant portion of the
wall-clock time on C++ compilation. The first-run improvement ranges from
about 33 % to 61 % across the two machines.</li>
On the cached run</strong>, both simulators reuse a previously built native binary,
so the comparison is between the GCC-optimized output of each toolchain. Veryl
is still consistently faster.</li>
Across CPU generations</strong>, the gap is larger on the older Threadripper
1950X (Zen 1) than on the Xeon Gold 6434 (Sapphire Rapids) — the smallest
cached-run cases shrink to 4–8 % on Sapphire Rapids but stay at 24–49 % on
Zen 1. We suspect Verilator's generated C++ is more sensitive to older
microarchitectures than the Veryl backends.</li>
</ul>
Veryl is faster than Verilator in both modes: substantially on the first run,
and more modestly on the cached run. Most edit-compile-run cycles during
development are dominated by the first-run number. Once a simulation runs long
enough — regression sweeps, full OS boots — the cached-run number takes over.</p>
What's next</h2>
The simulator is still under active development. We plan to extend the benchmark
to other CPU architectures and a wider range of designs, and to publish the
benchmark setup so the numbers can be reproduced.</p>


Announcing Veryl 0.20.0
2026-05-01T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.20.0.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
Breaking Changes</h1>
To migrate some syntax changes, veryl migrate</code> can be used:</p>

// Check how changes will be applied
</span>$ veryl migrate --check
</span>
</span>// Migrate
</span>$ veryl migrate
</span></code></pre>
</details>
Remove type specification on for</code> iterator #2516</a>
</h2>
The iterator variable in for</code> no longer accepts a type specification.
i32</code> is always used as the iterator type, which is more than sufficient for any
practical hardware loop bound and matches the syntax of generate for</code>.</p>
To migrate, drop the type annotation on the iterator. veryl migrate</code> rewrites this
automatically.</p>
//</span> before
</span>for </span>i: </span>u32 </span>in </span>0..10 {
</span>    a[i] = '0;
</span>}
</span>
</span>//</span> after
</span>for </span>i </span>in </span>0..10 {
</span>    a[i] = '0;
</span>}
</span></code></pre>
$tb::reset_gen</code> takes a clk</code> port #2574</a>
</h2>
$tb::reset_gen</code> now binds to its clock at instantiation time instead of receiving the
clock as an argument to each assert</code> call. Reset timing is always bound to a specific
clock in practice, so this makes the binding explicit at the connection site.</p>
To migrate, move the clock from the assert</code> argument list to the reset_gen</code> instance
port list.</p>
//</span> before
</span>inst </span>rst: $tb::reset_gen();
</span>
</span>initial</span> {
</span>    rst.assert(clk);
</span>    </span>//</span> ...
</span>}
</span>
</span>//</span> after
</span>inst </span>rst: $tb::reset_gen(clk);
</span>
</span>initial</span> {
</span>    rst.assert();
</span>    </span>//</span> ...
</span>}
</span></code></pre>
New Language Features</h1>
Type inference #2478</a>
</h2>
Type annotations on let</code>, const</code>, and var</code> declarations are now optional.
The type is inferred from the right-hand side expression, or for var</code> declarations,
from the first subsequent assignment.</p>
module </span>ModuleA {
</span>    </span>let </span>_a: </span>logic</span><8> = 0;
</span>
</span>    </span>//</span> Variable reference: type copied from the referenced variable.
</span>    </span>let </span>_b = _a;
</span>
</span>    </span>//</span> Sized literal: type implied by the literal itself.
</span>    </span>let </span>_c = 8'd255;
</span>
</span>    </span>//</span> const declarations also support inference.
</span>    </span>const </span>_D = 16'd100;
</span>
</span>    </span>//</span> var without annotation: inferred from the first assignment,
</span>    </span>//</span> including assignments inside always_comb blocks.
</span>    </span>var </span>_e;
</span>    </span>always_comb</span> {
</span>        _e = _a;
</span>    }
</span>}
</span></code></pre>
Introduce gen</code> declaration #2412</a>
</h2>
A new gen</code> declaration lets generic modules compute values — including derived
types — that can themselves be passed as generic arguments to inner instances.</p>
module </span>ModuleA::<W: </span>u32</span>, T: </span>type</span>> (
</span>    a: </span>output logic</span><W>,
</span>    b: </span>output </span>T       ,
</span>) {
</span>    </span>always_comb</span> {
</span>        a = '0;
</span>        b = '0;
</span>    }
</span>}
</span>
</span>module </span>ModuleB::<A: </span>u32</span>, B: </span>u32</span>, C: </span>u32</span>> {
</span>    gen W: </span>u32</span>  = A + B;
</span>    gen T: </span>type</span> = </span>logic</span><C>;
</span>
</span>    </span>inst </span>u: ModuleA::<W, T> (a: _, b: _);
</span>}
</span></code></pre>
New Tool Features</h1>
Logic synthesis support #2553</a>
</h2>
veryl synth</code> performs a lightweight gate-level synthesis directly from the toolchain
and reports area, critical-path timing, and power for the chosen top module.</p>
$ veryl synth --top Counter
</span>synth: Counter — 137 gates, 32 FFs
</span>library: SKY130 (SkyWater 130nm) / sky130_fd_sc_hd / tt_025C_1v80
</span>summary:
</span>  area:        1542.50 um²  (comb 822.50, seq 720.00)
</span>  timing:        0.540 ns       6 levels  r_cnt[15] → r_cnt[24]
</span>  power:         0.0990 mW   (leak 0.0001 mW, dyn 0.0989 mW)
</span>                 @ f_clk = 100 MHz, activity = 0.10
</span></code></pre>
Cell area, delay, and power figures are calibrated against public Liberty data from
open PDKs — SKY130 (SkyWater 130nm), ASAP7, GF180MCU, and IHP SG13G2 — so
estimates are based on real silicon ratios rather than abstract gate counts.
The numbers are intended as reference values for early-stage exploration, not signoff.</p>
SystemVerilog → Veryl translator #2480</a>
</h2>
veryl translate</code> converts SystemVerilog source files to equivalent Veryl, helpful for
incrementally migrating existing designs.</p>
$ veryl translate counter.sv
</span>$ ls counter.veryl
</span>counter.veryl
</span></code></pre>
Improve $assert</code> / $assert_continue</code> in testbench #2578</a>
</h2>
Native testbench assertions now report values and source locations on failure,
making test debugging significantly easier.</p>
Configurable newline style #2470</a>
</h2>
The formatter and the SystemVerilog translator now preserve the newline style of the
input file by default. Files originally written with CRLF stay CRLF after formatting
or translation, instead of being silently rewritten to LF. The behavior is
configurable via format.newline_style</code> in Veryl.toml</code>.</p>
New Standard Library</h1>
Add utility functions #2444</a>
 #2447</a>
 #2451</a>
 #2577</a>
</h2>
The following utility functions have been added under $std::utils</code>:</p>

min</code>, max</code> — element-wise minimum/maximum</li>
zero_extend</code>, one_extend</code>, sign_extend</code>, truncate</code> — width manipulation primitives</li>
select_*</code>, dispatch_*</code> — mux/demux building blocks usable outside of the mux</code> and demux</code> modules</li>
clog2_clipped</code> — a clipped variant of clog2</code> that stays well-defined for small ranges</li>
</ul>
Other Changes</h1>
Check out everything that changed in Release v0.20.0</a>.</p>


Announcing Veryl 0.19.1
2026-04-01T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.19.1.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
New Language Features</h1>
Infer clock domain #2400</a>
</h2>
Variables without explicit clock domain annotation can now be inferred from their context.
For example, when a variable is assigned from a signal with a known clock domain, the variable's domain is automatically inferred.</p>
module </span>ModuleA (
</span>    i_clk_a: </span>input</span>  'a </span>clock</span>,
</span>    i_rst_a: </span>input</span>  'a </span>reset</span>,
</span>    i_dat_a: </span>input</span>  'a </span>logic</span>,
</span>    o_dat_a: </span>output</span> 'a </span>logic</span>,
</span>) {
</span>    </span>var </span>x: </span>logic</span>;
</span>    </span>assign </span>x = i_dat_a;   </span>//</span> x is inferred as 'a domain
</span>    </span>assign </span>o_dat_a = x;
</span>}
</span></code></pre>
Support global function #2366</a>
</h2>
Functions can now be defined at the project root (outside of module</code>, interface</code>, and package</code>).
Global functions support generic type parameters and public visibility via pub</code>.</p>
pub function </span>add::<W: </span>u32</span>> (
</span>    a: </span>input logic</span><W>,
</span>    b: </span>input logic</span><W>,
</span>) -> </span>logic</span><W> {
</span>    </span>return </span>a + b;
</span>}
</span>
</span>module </span>ModuleA #(
</span>    </span>param </span>WIDTH: </span>u32</span> = 8,
</span>) (
</span>    i_a: </span>input  logic</span><WIDTH>,
</span>    i_b: </span>input  logic</span><WIDTH>,
</span>    o_c: </span>output logic</span><WIDTH>,
</span>) {
</span>    </span>assign </span>o_c = add::<WIDTH>(i_a, i_b);
</span>}
</span></code></pre>
Allow to specify multiple modports as default modport target #2306</a>
</h2>
Multiple modports can now be specified as default modport targets using ..same()</code> or ..converse()</code>.</p>
interface </span>InterfaceA {
</span>    </span>var </span>a: </span>u32</span>;
</span>    </span>var </span>b: </span>u32</span>;
</span>    </span>modport </span>mp_a { a: </span>input</span> }
</span>    </span>modport </span>mp_b { b: </span>input</span> }
</span>    </span>modport </span>mp_ab {
</span>        ..</span>same</span>(mp_a, mp_b)
</span>    }
</span>}
</span></code></pre>
Copy imported functions from target modports of same</code> default member #2326</a>
</h2>
When using ..same()</code> to inherit from another modport, imported functions from the target modport are now automatically copied.</p>
interface </span>InterfaceA {
</span>    </span>var </span>a: </span>u32</span>;
</span>    </span>modport </span>mp_a {
</span>        a: </span>input</span>,
</span>        </span>import </span>get_a(),
</span>    }
</span>    </span>modport </span>mp_b {
</span>        ..</span>same</span>(mp_a)   </span>//</span> get_a() is automatically copied
</span>    }
</span>}
</span></code></pre>
Add positive integer types #2281</a>
</h2>
New integer types p8</code>, p16</code>, p32</code>, and p64</code> are introduced, which restrict values to positive numbers only.</p>
module </span>ModuleA {
</span>    </span>const </span>X: p32 = 10;
</span>}
</span></code></pre>
New Tool Features</h1>
Minimal support of Veryl native testbench #2338</a>
</h2>
Veryl now supports native testbench syntax. You can write testbenches directly in Veryl using $tb::clock_gen</code> and $tb::reset_gen</code> for clock and reset generation, and initial</code> blocks for test scenarios.</p>
#[test(test_counter)]
</span>module </span>test_counter {
</span>    </span>inst </span>clk: $tb::clock_gen;
</span>    </span>inst </span>rst: $tb::reset_gen;
</span>
</span>    </span>var </span>cnt: </span>logic</span><32>;
</span>
</span>    </span>inst </span>dut: Counter (
</span>        clk: clk,
</span>        rst: rst,
</span>        cnt: cnt,
</span>    );
</span>
</span>    </span>initial</span> {
</span>        rst.assert(clk);
</span>        clk.next  (10);
</span>        $assert   (cnt == 32'd10);
</span>        $finish   ();
</span>    }
</span>}
</span></code></pre>
Note that the native simulator used for native tests may still contain bugs. Please use with caution. If you find any bugs, please report them via GitHub Issues</a>.</p>
Add #[ignore]</code> attribute for #[test]</code> #2418</a>
</h2>
Tests can now be marked with #[ignore]</code> to skip them during test execution.</p>
#[test(test_counter)]
</span>#[ignore]
</span>module </span>test_counter {
</span>}
</span></code></pre>
Documentation test by WaveDrom #2363</a>
</h2>
WaveDrom timing diagrams in documentation comments can now be tested by using the wavedrom,test</code> tag. This validates the WaveDrom JSON syntax at build time.</p>
//</span>/ ```wavedrom,test
</span>//</span>/ { "signal": [{ "name": "clk", "wave": "p..." }] }
</span>//</span>/ ```
</span>pub module </span>ModuleA {}
</span></code></pre>
Playground improvements</h2>
The Veryl Playground</a> has been redesigned with the following improvements:</p>


UI overhaul with dark/light theme support</li>
Auto-save of code to browser storage</li>
Shareable link generation</li>
Simulation with waveform viewer and VCD download</li>
</ul>
Other Changes</h1>
Check out everything that changed in Release v0.19.1</a>.</p>


Announcing Veryl 0.19.0
2026-03-04T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.19.0.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
Breaking Changes</h1>
To migrate some syntax changes, veryl migrate</code> can be used:</p>

// Check how changes will be applied
</span>$ veryl migrate --check
</span>
</span>// Migrate
</span>$ veryl migrate
</span></code></pre>
</details>
Report error for calling function which has references to variables defined after the call #2240</a>
 #2284</a>
</h2>
The following code worked until Veryl 0.19.0, but these code sometimes caused false-positive warning/error.
To resolve this issue, Veryl 0.19.0 reports error for these code.</p>
always_comb</span> {
</span>    a = func(); </span>//</span> function call before `b` definition
</span>}
</span>
</span>var </span>b: </span>logic</span>;
</span>function </span>func() -> </span>logic</span> {
</span>    </span>return </span>b;
</span>}
</span></code></pre>
The following code is still valid, because b</code> is defined before the function call.</p>
var </span>b: </span>logic</span>;
</span>always_comb</span> {
</span>    a = func(); </span>//</span> function call after `b` definition
</span>}
</span>
</span>function </span>func() -> </span>logic</span> {
</span>    </span>return </span>b;
</span>}
</span></code></pre>
New Language Features</h1>
Support inferable enum width #2199</a>
</h2>
The type of enum can be omitted like enum A {}</code>, but in this case the base type of enum is fixed to logic</code>.
We introduced a new syntax to specify the base type of enum like below.</p>
enum </span>A: </span>bit</span><_> {
</span>   X,
</span>   Y,
</span>}
</span>
</span>enum </span>B: </span>logic</span><_> {
</span>   X,
</span>   Y,
</span>}
</span></code></pre>
New Standard Library</h1>
Add interface definition of AXI stream as std library #2208</a>
</h2>
The interface definition of AXI stream is added.</p>
https://std.veryl-lang.org/axi4_stream_if.html</a></p>
Other Changes</h1>
Check out everything that changed in Release v0.19.0</a>.</p>


Announcing Veryl 0.18.0
2026-02-02T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.18.0.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
Breaking Changes</h1>
To migrate some syntax changes, veryl migrate</code> can be used:</p>

// Check how changes will be applied
</span>$ veryl migrate --check
</span>
</span>// Migrate
</span>$ veryl migrate
</span></code></pre>
</details>
Allow concatenation assignment in always, and add block</code> keyword #2175</a>
</h2>
Bit concatenation in left-hand side of always_comb</code> and always_ff</code> is allowed now.</p>
always_comb</span> {
</span>    {a, b} = 1;
</span>}
</span></code></pre>
On the other hand, this feature conflicts the existing statement grouping syntax by {}</code>.
So new block</code> keyword is introduced to avoid the conflicts.</p>
always_comb</span> {
</span>    </span>//</span> grouping by `{}` is not allowed
</span>    </span>//</span>{
</span>    </span>//</span>    a = 1;
</span>    </span>//</span>    b = 1;
</span>    </span>//</span>}
</span>
</span>    </span>block</span> {
</span>        a = 1;
</span>        b = 1;
</span>    }
</span>}
</span></code></pre>
Split bool</code> type to bbool</code> and lbool</code> types #2186</a>
</h2>
Using bool</code> in const context caused assigning 4-state variable to 2-state variable because bool</code> is type alias of logic<1></code>.</p>
const </span>flag: </span>bool</span> = </span>true</span>;
</span>const </span>X: </span>u32</span> = </span>if </span>flag ? 10 : 20; </span>//</span> 4-state variable is used in const context
</span></code></pre>
To avoid this mismatch, bbool</code> and lbool</code> is introduced instead of bool</code>.</p>

bbool</code>: the type alias of bit<1></code></li>
lbool</code>: the type alias of logic<1></code></li>
</ul>
const </span>flag: </span>bbool</span> = </span>true</span>;
</span>const </span>X: </span>u32</span> = </span>if </span>flag ? 10 : 20;
</span></code></pre>
New Language Features</h1>
#[allow(unassign_variable)]</code> attribute #2147</a>
</h2>
By IR-based semantic analyzer, unassign check was enhanced.
If you want to disable the check, #[allow(unassign_variable)]</code> attribute can be used.</p>
#[allow(unassign_variable)]
</span>module </span>Module A {
</span>}
</span></code></pre>
New Tool Features</h1>
Introduce IR-based semantic analyzer #2005</a>
</h2>
The new IR-based semantic analyzer is introduced.
Please refer the following post for the detailed changes.</p>
Semantic Analysis based on Intermediate Representation</a></p>
Other Changes</h1>
Check out everything that changed in Release v0.18.0</a>.</p>


Announcing Verylup 0.1.12
2026-01-23T00:00:00+00:00
The Veryl team has published a new release of Verylup, 0.1.12.
Verylup is the official toolchain installer of Veryl.
It installs the latest Veryl toolchain and eases to update and switch the toolchains.</p>
If you have a previous version of Verylup installed, getting Verylup 0.1.12 is as easy as stopping any programs which may be using Verylup (e.g. closing your IDE) and running:</p>
verylup update
</span></code></pre>
If you don't have it already, please refer Getting Started</a>.</p>
Important Notice</h1>
verylup install nightly</code> failure</h2>
From Verylup 0.1.10 to 0.1.11, verylup install nightly</code> fails like below if the nightly installation is the first time.</p>
$ verylup install nightly
</span>Error: No such file or directory (os error 2)
</span></code></pre>
Please update to Verylup 0.1.12 if you encountered this issue.</p>
Other Changes</h1>
Check out everything that changed in Release v0.1.12</a>.</p>


Semantic Analysis based on Intermediate Representation
2026-01-20T00:00:00+00:00
We plan to introduce a new semantic analyzer based on intermediate representation at the next release.
This enables the following features.</p>

Bit-wise latch / unassign detection</li>
More detailed type check considering parameter override and generics</li>
Performance improvement</li>
</ul>
For example, the new analyzer can detect the following error.</p>
var </span>a: </span>logic</span><2>;
</span>always_comb</span> {
</span>    </span>if </span>x {
</span>        a = 1;
</span>    } </span>else</span> {
</span>        </span>//</span> a[0] is latch error
</span>        a[1] = 1;
</span>    }
</span>}
</span></code></pre>
About performance improvement, we got the following results.</p>

Small testcase (unit tests of Veryl compiler): 448ms to 330ms (+36%)</li>
Large testcase (A real project with 66K lines): 68s to 14s (+386%)</li>
</ul>
Additionally, the introduced intermediate representation can be used for native Veryl simulator.
We plan to work on implementing it after releasing the new version.</p>
Important change</h2>
The new analyzer can handle several errors which can't be detected by the previous version.</p>
Some tools, including Verilator, ignore these error, so existing Veryl files may contain this error.
In that case, you'll need to fix your code, as it will no longer compile after an update to the Veryl compiler.</p>
Here are some common errors we see in Veryl code on GitHub:</p>
Refering before definition</h3>
In the following code, a</code> is referred before it's definition.</p>
let </span>b: </span>logic</span> = a;
</span>var </span>a: </span>logic</span>;
</span></code></pre>
The next version Veryl compiler detects the following error.</p>
Error: referring_before_definition ()
</span>
</span>  × a is referred before it is defined.
</span>   ╭─[.../test.veryl:2:20]
</span> 1 │ module ModuleA {
</span> 2 │     let b: logic = a;
</span>   ·                    ┬
</span>   ·                    ╰── Error location
</span> 3 │     var a: logic;
</span>   ╰────
</span>  help: move definition before reference point
</span></code></pre>
Multiple assignment of interface member</h3>
In the following code, p</code> is driven by both u0</code> and u1</code>.
Actually u0</code> only drives p.x</code> and u1</code> only drives p.y</code>, so it is not multiple assignment exactly.
However new Veryl compiler treats this case as multiple assignment.
This is because determining multiple assignment depending on the module implementation requires traversing the entire instance hierarchy,
which is expensive and makes the location of the error and the cause of the error far apart, making the error message difficult to interpret.</p>
In this case, you can divide master</code> modport into master_x</code> and master_y</code> to resolve this error.</p>
interface </span>InterfaceA {
</span>    </span>var </span>x: </span>logic</span>;
</span>    </span>var </span>y: </span>logic</span>;
</span>
</span>    </span>modport </span>master {
</span>        x: </span>output</span>,
</span>        y: </span>output</span>,
</span>    }
</span>}
</span>
</span>module </span>ModuleA {
</span>    </span>inst </span>p: InterfaceA;
</span>
</span>    </span>inst </span>u0: ModuleB ( p, );
</span>    </span>inst </span>u1: ModuleC ( p, );
</span>}
</span>
</span>module </span>ModuleB (
</span>    p: </span>modport </span>InterfaceA::master,
</span>) {
</span>    </span>assign </span>p.x = 0;
</span>}
</span>
</span>module </span>ModuleC (
</span>    p: </span>modport </span>InterfaceA::master,
</span>) {
</span>    </span>assign </span>p.y = 0;
</span>}
</span></code></pre>
Release plan</h2>
We plan to release the next version including the new analyzer at the beginning of Feb. 2026.
If you want to try it before the release, you can use nightly compiler like below after 2026-01-22 02:00 (UTC).</p>
$verylup install nightly
</span>$veryl +nightly --version
</span>veryl 0.17.2-nightly (f63dc84 2026-01-20)
</span></code></pre>
The new analyzer may introduce false positive error because it replaces the whole analyzer by new code.
If you find any unexpected behaviour, please open an issue</a> on GitHub.</p>


Announcing Veryl 0.17.2
2026-01-05T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.17.2.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
New Tool Features</h1>
Zed extension #2139</a>
</h2>
Veryl extension for Zed</a> is added.
It supports syntax highlighting and language server.
The extension can be installed through the following URL.</p>
https://zed.dev/extensions/veryl</a></p>
Other Changes</h1>
Check out everything that changed in Release v0.17.2</a>.</p>


Announcing Veryl 0.17.1
2025-12-01T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.17.1.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
New Tool Features</h1>
DSim runner #2034</a>
</h2>
Altair DSim</a> support for veryl test</code> is added.</p>
$ veryl test --sim dsim
</span></code></pre>
vertical_align</code> format option #2065</a>
</h2>
By default, veryl fmt</code> formats with keeping vertial alignment like below.</p>
let a : logic    = 1;
</span>let aa: logic<2> = 1;
</span></code></pre>
However, this causes unexpected differences by revision control systems like git.</p>
let a  : logic    = 1; // not changed logically, but diff occurs
</span>let aa : logic<2> = 1; // not changed logically, but diff occurs
</span>let aaa: logic<2> = 1;
</span></code></pre>
To prevent this behaviour, you can use vertical_align</code> option.</p>
[format]
</span>vertical_align </span>= </span>false
</span></code></pre>
New Standard Library</h1>
Basic synchronizer implementation #2036</a>
</h2>
The default implementation of std::synchronizer</code>, which uses single-bit FF scheme, is added.</p>
https://std.veryl-lang.org/synchronizer_basic.html</a></p>
Other Changes</h1>
Check out everything that changed in Release v0.17.1</a>.</p>


Announcing Verylup 0.1.11
2025-11-19T00:00:00+00:00
The Veryl team has published a new release of Verylup, 0.1.11.
Verylup is the official toolchain installer of Veryl.
It installs the latest Veryl toolchain and eases to update and switch the toolchains.</p>
If you have a previous version of Verylup installed, getting Verylup 0.1.11 is as easy as stopping any programs which may be using Verylup (e.g. closing your IDE) and running:</p>
verylup update
</span></code></pre>
If you don't have it already, please refer Getting Started</a>.</p>
New Features</h1>
Custom CA bundle support for downloads</h2>
In environments behind a proxy that re-signs HTTPS traffic with an enterprise root CA, custom CA bundle support is necessary.
verylup becomes to load a custom CA bundle through SSL_CERT_FILE</code> environment variable or OS-dependent CA stores.</p>
Other Changes</h1>
Check out everything that changed in Release v0.1.11</a>.</p>


Announcing Verylup 0.1.10
2025-11-05T00:00:00+00:00
The Veryl team has published a new release of Verylup, 0.1.10.
Verylup is the official toolchain installer of Veryl.
It installs the latest Veryl toolchain and eases to update and switch the toolchains.</p>
If you have a previous version of Verylup installed, getting Verylup 0.1.10 is as easy as stopping any programs which may be using Verylup (e.g. closing your IDE) and running:</p>
verylup update
</span></code></pre>
If you don't have it already, please refer Getting Started</a>.</p>
New Features</h1>
VersionReq syntax support</h2>
VersionReq syntax like +0.16</code> instead of complete version +0.16.0</code> can be used.
If +0.16</code> is specified, the latest version in 0.16.x</code> is selected.</p>
$ veryl +0.16.0 --version
</span>veryl 0.16.0 (56a6056 2025-05-05)
</span>$ veryl +0.16 --version
</span>veryl 0.16.5 (617da3e 2025-10-06)
</span></code></pre>
aarch64-windows support</h2>
aarch64-windows</code> platform support is added.</p>
Version check of nightly channel</h2>
Before this version, verylup update</code> always downloaded nightly build.
Now version checking of nightly channel is added, and verylup update</code> becomes faster when there is no update of nightly build.</p>
$ verylup update
</span>[INFO ]     checking toolchain: latest (up-to-date)
</span>[INFO ]     checking toolchain: nightly (up-to-date)
</span>[INFO ]     checking verylup: 0.1.10 (up-to-date)
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.1.10</a>.</p>


Announcing Veryl 0.17.0
2025-11-04T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.17.0.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
Breaking Changes</h1>
To migrate some syntax changes, veryl migrate</code> can be used:</p>

// Check how changes will be applied
</span>$ veryl migrate --check
</span>
</span>// Migrate
</span>$ veryl migrate
</span></code></pre>
</details>
Remove ===</code> and !==</code> operator #2006</a>
</h2>
===</code> and !==</code> operator are removed because they are not synthesizable.
Please use ==</code> and !=</code> instead of them.</p>
Remove ^~</code> operator #2008</a>
</h2>
Both ~^</code> and ^~</code> was XNOR operator.
Now ^~</code> operator is removed and XNOR operator is ~^</code>.
This change improves consistency with NAND (~&</code>) and NOR (~|</code>) operator.
After this change, ^~</code> is interpreted as combination of ^</code> and ~</code> like below.</p>
x ^~ y </span>//</span> x XOR (NOT y)
</span>^~ x   </span>//</span> Reduction XOR (NOT x)
</span></code></pre>
New Tool Features</h1>
Add cocotb 2.0 support #1958</a>
</h2>
Cocotb 2.0</a> has been released and we have added support for it in veryl test</code>.</p>
Information</h1>
DOI of Veryl release</h2>
After this version, DOI (Digital Object Identifier) is added to all Veryl release.
If you refer Veryl in your paper, please use the following DOI.</p>

Concept DOI: https://doi.org/10.5281/zenodo.17518832</a></li>
v0.17.0 DOI: https://doi.org/10.5281/zenodo.17518833</a></li>
</ul>
Other Changes</h1>
Check out everything that changed in Release v0.17.0</a>.</p>


Update the Visual Studio Code extension
2025-10-16T00:00:00+00:00
Today we announce a new version of the Veryl extension for Visual Studio Code.
The new version has the complete same functionality as the previous version.
The only change is that the publisher is now the veryl-lang organization.</p>
Veryl extension for Visual Studio Code</a></p>
For existing Veryl developers using VS Code, the transition should be seamless:
the old release should automatically install the new extension and disable itself,
and moving forward all language features will be provided by the new extension.
You’re welcome to uninstall the original extension, which has been renamed to reflect its deprecated status.</p>
If you have any issues migrating, please send an issue</a>.</p>


Announcing Veryl 0.16.5
2025-10-06T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.16.5.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
New Features</h1>
This version doesn't contain new features.</p>
Other Changes</h1>
Check out everything that changed in Release v0.16.5</a>.</p>


Official Docker image
2025-10-01T00:00:00+00:00
The Veryl team has published the official Docker image of Veryl.
It can be used as the base image for your custormized image, GitLab CI/CD and so on.</p>
https://hub.docker.com/r/veryllang/veryl</a></p>
Additionally, this project was approved for "Docker-Sponsored Open Source program"</a>.
By collaborating with Docker Inc., unlimited pull rate is provided.</p>
Here is some examples to use the Docker image.</p>
docker</code> command</h2>
You can pull the docker image from veryllang/veryl</code>.</p>
$ docker pull veryllang/veryl
</span></code></pre>
Dockerfile</code></h2>
If you want to use the official image as a base of your Docker image, the following FROM</code> directive can be used.</p>
FROM veryllang/veryl:latest
</span></code></pre>
GitLab CI/CD</h2>
The following is an example of .gitlab-ci.yml</code> for GitLab</a> CI/CD.</p>
image</span>: </span>"</span>veryllang/veryl</span>"
</span>
</span>build</span>:
</span>  </span>stage</span>: </span>build
</span>  </span>script</span>:
</span>    - </span>veryl build
</span>
</span>fmt</span>:
</span>  </span>stage</span>: </span>build
</span>  </span>script</span>:
</span>    - </span>veryl fmt --check
</span></code></pre>


Additional Maintainer
2025-09-16T00:00:00+00:00
This project was started as a personal project of Naoya Hatta ( dalance</a> ), and all administrator privileges are owned by him.
This status is called "Bus factor 1", it means the project stops completely if he leaves this project unexpectedly.</p>
To resolve this issue, Taichi Ishitani ( taichi-ishitani</a> ) was added as a maintainer to this project.
He is the 2nd place of the contributor list, and implements many language features.</p>
Now we share almost all privileges, including GitHub organization, veryl-lang.org domain, and so on.
This significantly reduced the risk of the project being stopped due to unforeseen circumstances.
Naoya Hatta will contribute to this project as the language owner continuously.</p>


Announcing Verylup 0.1.9
2025-09-12T00:00:00+00:00
The Veryl team has published a new release of Verylup, 0.1.9.
Verylup is the official toolchain installer of Veryl.
It installs the latest Veryl toolchain and eases to update and switch the toolchains.</p>
If you have a previous version of Verylup installed, getting Verylup 0.1.9 is as easy as stopping any programs which may be using Verylup (e.g. closing your IDE) and running:</p>
verylup update
</span></code></pre>
If you don't have it already, please refer Getting Started</a>.</p>
Important Notice</h1>
Verylup 0.1.7 unexpectedly disabled the self-update feature by default. If you see the following message at verylup update</code>, please update to Verylup 0.1.8 manually.</p>
$ verylup update
</span>...
</span>[INFO ]  self-update is disabled
</span></code></pre>
New Features</h1>
VERYLUP_HOME</code> environment variable support</h2>
By default, verylup uses the data directory defined by XDG Base Directory Specification</a> to store Veryl toolchains.
This directory is defined every users, therefore it cannot be share by some users.</p>
This behaviour causes a problem in cases like creating container image, in which the user installing Veryl and the actual user are different.
To resolve the issue, VERYLUP_HOME</code> environment variable can be used.
If it is defined, verylup installs Veryl toolchains under the VERYLUP_HOME</code> directory.</p>
Add toolchain</code> option for setup</h2>
If you want to specify the toolchain at verylup setup</code>, --toolchain</code> option can be used.</p>
verylup setup --toolchain 0.16.4
</span>verylup setup --toolchain nightly
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.1.9</a>.</p>


Announcing Veryl 0.16.4
2025-09-08T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.16.4.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
New Language Features</h1>
Support embed identifier #1836</a>
</h2>
If you want to refer Veryl's identifier in embed</code> declaration, the identifier can be placed with \{</code> and \}</code>.
This is useful when you want to use complex identifiers such as generics.</p>
module </span>ModuleA {
</span>    </span>embed</span> (inline) sv{{{
</span>        \{ ModuleB::<1> \} u_b ();
</span>    }}}
</span>}
</span></code></pre>
Support bind declaration #1887</a>
</h2>
bind</code> declaration is supported to specify to bind a module to another module.</p>
bind </span>ModuleA <- u: ModuleB (
</span>  i_clk: i_clk,
</span>  i_rst: i_rst,
</span>  i_a  : a    ,
</span>  o_b  : b    ,
</span>);
</span></code></pre>
New Tool Features</h1>
Add error_count_limit</code> build option #1864</a>
</h2>
By default, Veryl compiler prints all errors. To specify maximum error count, error_count_limit</code> can be used.</p>
[build]
</span>error_count_limit </span>= </span>10
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.16.4</a>.</p>


GitLab supports syntax highlighting of Veryl
2025-09-03T00:00:00+00:00
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
GitLab 18.3, which was released at 2025/08/21, includes syntax highlighting support of Veryl.
This feature can be used for on-premise environment, and it was already reflected to https://gitlab.com</a>.</p>



Announcing Veryl 0.16.3
2025-08-04T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.16.3.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
New Language Features</h1>
Support omittable RHS value of proto param #1778</a>
</h2>
In proto modules, the right-hand side value of param</code> / const</code> is not necessary.
So it becomes to be omittable.</p>
proto module </span>ModuleA #(
</span>    </span>param </span>A: </span>u32</span> = 0,
</span>    </span>param </span>B: </span>u32</span>    , </span>//</span> RHS value can be omitted
</span>);
</span></code></pre>
Support for loop in descending order #1783</a>
</h2>
rev</code> keyword is introduced to indicate loop in descending order.</p>
for </span>i: </span>i32 </span>in rev </span>0..32 {
</span>}
</span>
</span>//</span> Generated SV
</span>//</span> for (int i = 32 - 1; i >= 0; i--) begin
</span>//</span> end
</span></code></pre>
Add fmt(skip)</code> attribute #1804</a>
</h2>
fmt(skip)</code> attribute is introduced to indicate the following block is not formatted by veryl fmt</code>.
It can be added to module, interface and package.</p>
#[fmt(skip)]
</span>module </span>ModuleA {
</span>}
</span></code></pre>
New Tool Features</h1>
Incremental build support #1823</a>
</h2>
In large projects, veryl build</code> sometimes takes a long time.
To accelarate such case, incremental build is introduced.
If incremental build is enabled, Veryl compiler traces the last modified time and generated time of files,
and re-generates only files related modified source code.</p>
The reliability of tracing is not yet high, so incremental build is not enabled by default.
To enable it, you can specify in Veryl.toml</code> like below:</p>
[build]
</span>incremental </span>= </span>true
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.16.3</a>.</p>


Announcing Verylup 0.1.7
2025-07-22T00:00:00+00:00
The Veryl team has published a new release of Verylup, 0.1.7.
Verylup is the official toolchain installer of Veryl.
It installs the latest Veryl toolchain and eases to update and switch the toolchains.</p>
If you have a previous version of Verylup installed, getting Verylup 0.1.7 is as easy as stopping any programs which may be using Verylup (e.g. closing your IDE) and running:</p>
verylup update
</span></code></pre>
If you don't have it already, please refer Getting Started</a>.</p>
New Features</h1>
Add --no-self-update</code> option and no-self-update</code> feature support</h2>
If users don't have write permission for the verylup binary, various commands of verylup are failed.
For example, installing verylup through Linux distribution's packaging system causes this issue.</p>
To avoid this issue, the two option is provided.
--no-self-update</code> option can be used at verylup setup</code>.
This option disables self-update of verylup for users who executed verylup setup</code>.
This is for users who don't prefer self-update feature.</p>
verylup setup --no-self-update
</span></code></pre>
no-self-update</code> feature can be used at cargo build</code> or cargo install</code>.
This feature permanently disables self-update.
This is for Linux distribution's packaging.</p>
cargo build --release --features no-self-update
</span>cargo install verylup --features no-self-update
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.1.7</a>.</p>


Announcing Veryl 0.16.2
2025-07-08T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.16.2.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
New Language Features</h1>
Support reference to type defiend in existing package via proto package #1691</a>
</h2>
Proto typedefs are allowed to have their actual types. This allows a type symbol defined in a different package to be imported into the proto package and referenced from other components through it.</p>
package </span>FooPkg {
</span>    </span>struct </span>Foo {
</span>        foo: </span>logic</span>,
</span>    }
</span>}
</span>
</span>proto package </span>BarProtoPkg {
</span>    </span>type </span>Foo = FooPkg::Foo;
</span>}
</span>
</span>package </span>BarPkg </span>for </span>BarProtoPkg {
</span>    </span>type </span>Foo = FooPkg::Foo;
</span>}
</span>
</span>module </span>ModuleA::<PKG: BarProtoPkg> {
</span>    </span>var </span>_foo    : PKG::Foo;
</span>    </span>assign </span>_foo.foo = 0;
</span>}
</span>
</span>module </span>ModuleB {
</span>    </span>inst </span>u: ModuleA::<BarPkg>;
</span>}
</span></code></pre>
Add const declarations to StatementBlockItems #1695</a>
</h2>
const</code> declaration can be used in statement blocks.</p>
function </span>foo () -> </span>u32</span> {
</span>    </span>const </span>bar: </span>u32</span> = 2;
</span>    </span>return </span>bar;
</span>}
</span></code></pre>
Support embed declaration in component declaration #1712</a>
</h2>
embed</code> declaration with sv</code> block can be used in component declaration like module, interface and package.</p>
module </span>ModuleA {
</span>    </span>embed</span> (inline) sv{{{
</span>        </span>initial </span>begin
</span>            $display(</span>"hello"</span>);
</span>        end
</span>    }}}
</span>}
</span></code></pre>
New Tool Features</h1>
Merge Waveform Render into Veryl VS Code Extension #1713</a>
</h2>
VSCode Extension supports preview of waveform in documentation comments.</p>

Add support for including additional files for tests #1718</a>
 #1729</a>
</h2>
Additional files for test can be specified by include_files</code>. For example, it can be used to specify HEX files which are read by $readmemh</code>.</p>
[test]
</span>include_files </span>= [</span>"</span>test.hex</span>"</span>]
</span></code></pre>
Allow to specify multiple source directories #1747</a>
</h2>
Multiple source directories can be specified via sources</code> instead of source</code>.
source</code> becomes deprecated, and will be removed after a few versions.</p>
[build]
</span>sources </span>= [</span>"</span>rtl</span>"</span>, </span>"</span>tb</span>"</span>]
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.16.2</a>.</p>


Announcing Verylup 0.1.6
2025-07-08T00:00:00+00:00
The Veryl team has published a new release of Verylup, 0.1.6.
Verylup is the official toolchain installer of Veryl.
It installs the latest Veryl toolchain and eases to update and switch the toolchains.</p>
If you have a previous version of Verylup installed, getting Verylup 0.1.6 is as easy as stopping any programs which may be using Verylup (e.g. closing your IDE) and running:</p>
verylup update
</span></code></pre>
If you don't have it already, please refer Getting Started</a>.</p>
New Features</h1>
Add proxy support</h2>
Verylup supports HTTP/SOCKS5 proxy.
By default, verylup refers system proxy configuration via the following environment variables:</p>

HTTPS_PROXY</code> / https_proxy</code></li>
ALL_PROXY</code> / all_proxy</code></li>
</ul>
If you want to specify proxy for verylup only, the following command can be used.</p>
verylup config set proxy socks5://127.0.0.1:1086
</span></code></pre>
Add aarch64-linux support</h2>
Now verylup supports aarch64-linux. The supported platforms are below:</p>

x86_64-linux</li>
x86_64-mac</li>
x86_64-windows</li>
aarch64-linux</li>
aarch64-mac</li>
</ul>
Other Changes</h1>
Check out everything that changed in Release v0.1.6</a>.</p>


Announcing Veryl 0.16.1
2025-06-02T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.16.1.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
New Language Features</h1>
Support flattened array modport/instance #1566</a>
</h2>
Some EDA tools don't support multi-dimentional array modport/instance.
To support such tools, flatten_array_interface</code> can be used.</p>
[build]
</span>flatten_array_interface </span>= </span>true
</span></code></pre>
The following is an example of code generation.</p>

Veryl</li>
</ul>
inst </span>if_a: InterfaceA[2, 3];
</span></code></pre>

SystemVerilog</li>
</ul>
InterfaceA if_a[6]();
</span></code></pre>
Add a build option to hashed mangle-name #1614</a>
</h2>
If an generic instance has many arguments, the mangled name becomes too long.
To shorten such names, hashed_mangled_name</code> can be used.</p>
[build]
</span>hashed_mangled_name </span>= </span>true
</span></code></pre>
Example:</p>

Un-hashed name: prj___PkgA__0__1__2__3__4__5__6__7</code></li>
Hashed name: prj___PkgA__3894375d1deadabb</code></li>
</ul>
Other Changes</h1>
Check out everything that changed in Release v0.16.1</a>.</p>


Announcing Veryl 0.16.0
2025-05-05T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.16.0.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
Breaking Changes</h1>
To migrate some syntax changes, veryl migrate</code> can be used:</p>

// Check how changes will be applied
</span>$ veryl migrate --check
</span>
</span>// Migrate
</span>$ veryl migrate
</span></code></pre>
</details>
Keep directory hierarchy for target = {type = "directory"}</code> #1513</a>
</h2>
target = {type = "directory"}</code> caused to break files which have the same name and belong different source directory, because it forces all output files to a single directory.
To avoid this issue, the behaviour of this option is changed to keep directory hierarchy of source.</p>
Change clock domain annotation symbol to '</code> #1517</a>
</h2>
Clock domain annotation symbol was `</code> by parser restriction.
But it is changed to '</code> as the same as Rust's lifetime annotation by improving parser implementation.</p>
//</span> Before
</span>i_clk: </span>input </span>`a </span>clock</span>,
</span>
</span>//</span> After
</span>i_clk: </span>input</span> 'a </span>clock</span>,
</span></code></pre>
Unsupport enum</code> / struct</code> / union</code> declarations in interface declaration #1521</a>
</h2>
enum</code>, struct</code> and union</code> in interface declaration were removed because they can't be refered from the outside of the interface.
If you use them, please move them to a package.</p>
Typed generic boundary #1548</a>
</h2>
const</code> as generic boundary was removed, and typed generic boundary is introduced.
This is because const</code> can't express a boundary for enum</code>.
veryl migrate</code> converts all const</code> to u32</code> boundary.</p>
//</span> Before
</span>package </span>PkgA::<X: </span>const</span>, Y: </span>const</span>> {}
</span>
</span>//</span> After
</span>package </span>PkgA::<X: </span>u32</span>, Y: EnumX> {}
</span></code></pre>
Forbid last item with ifdef in comma-separated list #1572</a>
</h2>
The last item with ifdef</code> in comma-separated list becomes to be forbidden.
This is because adjusting last comma by complex ifdef</code> combination is difficult.</p>
module </span>ModuleA (
</span>    a: </span>input logic</span>,
</span>    #[ifdef(B)] </span>//</span> this `ifdef` is forbidden
</span>    b: </span>input logic</span>,
</span>) {}
</span></code></pre>
Forbid project name starting with __</code> #1580</a>
</h2>
A project name starting with __</code> becomes to be forbidden, because it is used for Veryl compiler internally.</p>
$ veryl new __a
</span>Error:   × project name "__a" is reserved by system
</span></code></pre>
New Language Features</h1>
elsif</code> / else</code> attribute #1453</a>
</h2>
elsif</code> and else</code> attribute can be used with ifdef</code> or ifndef</code>.</p>
always_comb</span> {
</span>    #[ifdef(DEFINE_A)]
</span>    a = 1;
</span>    #[elsif(DEFINE_B)]
</span>    b = 1;
</span>    #[</span>else</span>]
</span>    c = 1;
</span>}
</span></code></pre>
Proto alias declaration #1473</a>
</h2>
alias</code> can be used in proto declaration.</p>
proto package </span>ProtoPackageA {
</span>    </span>alias module </span>InstModule: ProtoModuleA;
</span>}
</span>package </span>PackageA::<M: ProtoModuleA> </span>for </span>ProtoPackageA {
</span>    </span>alias module </span>InstModule = M;
</span>}
</span></code></pre>
Modport expansion #1512</a>
</h2>
Some synthesis tools don't support modport</code> as ports of the top module or boundary of hiererchical synthesis.
For such cases, if #[expand(modport)]</code> is specified, Veryl compiler expands modport</code> of the module.</p>
#[expand(</span>modport</span>)]
</span>module </span>ModuleA (
</span>    slv_if: </span>modport </span>InterfaceA::slave ,
</span>    mst_if: </span>modport </span>InterfaceA::master,
</span>) {}
</span></code></pre>
Skip to write files if no change #1518</a>
</h2>
If the existing generated files have the same contents which Veryl compiler is trying to emit, writing files is skipped.
By this change, the compatibility with timestamp based tools like GNU make is improved.</p>
Default project structure #1531</a>
</h2>
As the default project structure, veryl new</code> will create the following file and directories.</p>
.gitignore
</span>Veryl.toml
</span>src/
</span>target/
</span></code></pre>
Interface prototype #1532</a>
</h2>
Interface prototype becomes to be supported like below:</p>
proto interface </span>InterfaceA {
</span>  </span>function </span>FuncA(a: </span>input logic</span>, b: </span>input logic</span>) -> </span>logic</span>;
</span>
</span>  </span>modport </span>mp {
</span>    FuncA: </span>import</span>,
</span>  }
</span>}
</span></code></pre>
u8</code>, u16</code>, i8</code> and i16</code> fixed types #1537</a>
</h2>
u8</code>, u16</code>, i8</code> and i16</code> become to be supported as primitive types.</p>
let </span>a: </span>u8</span>  = 0;
</span>let </span>a: </span>u16</span> = 0;
</span>let </span>a: </span>i8</span>  = 0;
</span>let </span>a: </span>i16</span> = 0;
</span></code></pre>
Use modport as function argument #1554</a>
</h2>
Now modport</code> can be used as function argument.
Veryl compiler expands these modport to separated variables.</p>
function </span>FunctionA (
</span>    slv_if: </span>modport </span>InterfaceA::slave ,
</span>    mst_if: </span>modport </span>InterfaceA::master,
</span>) {}
</span></code></pre>
AXI3, AXI4, AXI4-Lite interfaces and prototypes in Veryl standard library #1577</a>
</h2>
Generic AXI3, AXI4, AXI4-Lite interfaces are added in Veryl standard library.</p>
alias package </span>axi3_pkg = $std::axi3_pkg::<32, 4, 8>;
</span>
</span>module </span>ModuleA (
</span>    slv_if: </span>modport</span> $std::axi3_if::<axi3_pkg>::slave,
</span>) {}
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.16.0</a>.</p>


Call for publishing Veryl source code on GitHub
2025-04-16T00:00:00+00:00
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
This article is written to call you for publishing Veryl source code on GitHub.
By publishing your source code, even if it is very simple like just "Hello World", the followings become possible.
Please cooperate with us!</p>
Syntax highlighting support on GitHub</h2>
The criteria of adding a language to the syntax highlighting library of GitHub is defined like below:</p>

at least 2000 files per extension indexed in the last year (the number you see at the top of the search results), unless the extension is expected to only occur once per repo, then 200 files.</li>
with a reasonable distribution across unique :user/:repo</code> combinations assessed by manually and randomly clicking through the results.</li>
</ul>
The first means that at least 2000 *.veryl</code> files are necessary, and the second means that the bias to the specific repositories like veryl-lang/veryl</code> is excluded.
The current status is gathered periodically, and published at the following site.</p>
https://veryl-lang.org/statistics/</a></p>
Unexpected breaking change detection</h2>
The repository of Veryl compiler has some testcases to detect unexpected breaking changes, but they are insufficient to cover all cases.
So we are periodically gathering Veryl projects published on GitHub, and checking whether they are compiled successfully.
Along with increasing actual Veryl projects, various use cases become to be covered.</p>
The gathering tool and gathered DB is in the following repository.</p>
https://github.com/veryl-lang/discovery</a></p>


Announcing Veryl 0.15.0
2025-04-01T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.15.0.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
Breaking Changes</h1>
Simplify if expression notation #1457</a>
</h2>
If expression is a relpacement of conditional operator in SystemVerilog, but it is pretty long than conditional operator.
And the {}</code> is redundant because only single expression can be placed in {}</code>.
Therefore, the notation is changed to more simplified style like conditional operator.</p>
//</span> Before
</span>assign </span>a = </span>if </span>b { c } </span>else</span> { d };
</span>
</span>//</span> After
</span>assign </span>a = </span>if </span>b ? c : d;
</span></code></pre>
We added veryl migrate</code> to migrate this change automatically, because it will affect many existing codebase.</p>
// Check how changes will be applied
</span>$ veryl migrate --check
</span>
</span>// Migrate
</span>$ veryl migrate
</span></code></pre>
Change dependency syntax #1373</a>
</h2>
The notation of [dependencies]</code> section in Veryl.toml</code> is changed.
This is for multiple project support in a repository.</p>
#</span> Before
</span>"</span>https://github.com/veryl-lang/sample</span>" </span>= </span>"</span>0.1.0</span>"
</span>
</span>#</span> After
</span>veryl_sample </span>= {</span>github </span>= </span>"</span>veryl-lang/veryl_sample</span>"</span>, </span>version </span>= </span>"</span>0.1.0</span>"</span>}
</span></code></pre>
Remove export</code> declaration / ref</code> direction #1367</a>
 #1351</a>
</h2>
Veryl compiler can't resolve symbols correctly through export</code> declaration, so it is removed until the reasonable use case is found.</p>
ref</code> direction is removed because it can't be used in synthesizable RTL.</p>
New Language Features</h1>
Introduce connect</code> operation #1423</a>
</h2>
To simplify connection between interface, connect</code> operation is introduced.
All members of the interface are connected automatically.</p>
module </span>ModuleA (
</span>    mst_if: </span>modport </span>InterfaceA::master,
</span>    slv_if: </span>modport </span>InterfaceA::slave ,
</span>) {
</span>    </span>inst </span>bus_if: InterfaceA;
</span>
</span>    </span>connect </span>mst_if <> bus_if.slave;
</span>    </span>connect </span>slv_if <> bus_if.master;
</span>}
</span></code></pre>
Struct constructor support #1418</a>
</h2>
To initialize struct, Struct constructor can be used instead of assigning each members.
This is especially useful to initialize const</code> because it can't be assigned by each members.</p>
..default</code> specifier can speficy the default value for unspecified members in the struct.</p>
module </span>ModuleA {
</span>    </span>struct </span>Param {
</span>        a: </span>bit</span><10>,
</span>        b: </span>bit</span><10>,
</span>    }
</span>
</span>    </span>const </span>p: Param = Param'{
</span>        a: 10,
</span>        b: 10,
</span>    };
</span>
</span>    </span>const </span>q: Param = Param'{
</span>        a: 1,
</span>        ..</span>default</span>(0) </span>//</span> means `b: 0`
</span>    };
</span>}
</span></code></pre>
Introduce bool</code> type #1389</a>
</h2>
bool</code> is a type alias of logic<1></code> to express boolean.
true</code> and false</code> literal which express 1'b1</code> and 1'b0</code> can be used.</p>
module </span>ModuleA {
</span>    </span>const </span>a: </span>bool</span> = </span>true</span>;
</span>    </span>const </span>b: </span>bool</span> = </span>false</span>;
</span>}
</span></code></pre>
Support default clock and reset #1386</a>
</h2>
In some cases, there are some clocks, but only single clock is used in all always_ff</code>.
For such case, default</code> type modifier can be used to specify the default clock and reset explicitly.</p>
module </span>ModuleA (
</span>    i_clk   : </span>input clock</span>,
</span>    i_clk_en: </span>input logic</span>,
</span>) {
</span>    </span>let </span>clk: </span>`_ </span>default </span>clock</span> = i_clk & i_clk_en;
</span>
</span>    </span>var </span>a: </span>logic</span>;
</span>
</span>    </span>always_ff</span> {
</span>        a = 0;
</span>    }
</span>}
</span></code></pre>
Add same</code> direction to modport default member #1381</a>
</h2>
same</code> direction which copies all members of the existing modport can be used.</p>
interface </span>InterfaceA {
</span>    </span>var </span>a: </span>logic</span>;
</span>    </span>var </span>b: </span>logic</span>;
</span>    </span>var </span>c: </span>logic</span>;
</span>
</span>    </span>modport </span>master {
</span>        a: </span>output</span>,
</span>        b: </span>input</span> ,
</span>        c: </span>input</span> ,
</span>    }
</span>
</span>    </span>modport </span>driver {
</span>        b: </span>output</span>,
</span>        ..</span>same</span>(master)
</span>    }
</span>}
</span></code></pre>
Support module / interface / package alias #1342</a>
 #1374</a>
</h2>
To shorten long item with many generic parameters, alias</code> can be used.</p>
package </span>PkgA::<X: </span>const</span>, Y: </span>const</span>, Z: </span>const</span>> {}
</span>
</span>alias package </span>PkgA123 = PkgA::<1, 2, 3>;
</span></code></pre>
Introduce proto package #1336</a>
</h2>
As generic bound, proto package can be used.</p>
proto package </span>ProtoA {
</span>    </span>type </span>data_a;
</span>    </span>type </span>data_b;
</span>}
</span>
</span>package </span>PackageA::<A: </span>const</span>, B: </span>const</span>> </span>for </span>ProtoA {
</span>    </span>type </span>data_a = </span>logic</span><A>;
</span>    </span>type </span>data_b = </span>logic</span><B>;
</span>}
</span>
</span>module </span>ModuleA::<PKG: ProtoA> {
</span>    </span>let </span>_a: PKG::data_a = 0;
</span>}
</span></code></pre>
Function call with named argument #1452</a>
</h2>
Function call with named arguments can be used to make easy to see function with many arguments.</p>
module </span>ModuleA {
</span>    </span>function </span>FunctionA (
</span>        a: </span>input logic</span>,
</span>        b: </span>input logic</span>,
</span>        c: </span>input logic</span>,
</span>        d: </span>input logic</span>,
</span>    ) {}
</span>
</span>    </span>let </span>_a: </span>logic</span> = FunctionA(
</span>        a: 1,
</span>        b: 1,
</span>        c: 1,
</span>        d: 1,
</span>    );
</span>}
</span></code></pre>
New Tool Features</h1>
.build</code> directory</h2>
.build</code> directory to store build related information is created after veryl build</code>.
We recommend to add the following entry to your .gitignore</code>.</p>
.build/
</span></code></pre>
Add waveform format option / Implement waveform for cocotb #1388</a>
</h2>
To specify waveform format, waveform_format</code> field in Veryl.toml</code> is added.
Waveform dump support for cocotb is added too.</p>
[test]
</span>waveform_format </span>= </span>"</span>vcd</span>"  </span>#</span> or "fst"
</span></code></pre>
Add --check</code> option for veryl build</code> #1348</a>
</h2>
veryl build --check</code> can be used to check whether the generated files will be changed.</p>
Create git repo and default .gitignore</code> at veryl new/init</code> #1437</a>
</h2>
If git</code> command is available, veryl new</code> and veryl init</code> initialize the project directory as git repository, and put the default .gitignore</code>.</p>
Add fmt(compact)</code> attribute #1335</a>
</h2>
fmt(compact)</code> attribute enables compact formatting without newlines.</p>
module </span>ModuleA {
</span>    #[fmt(compact)]
</span>    {
</span>        </span>inst </span>u1: $sv::Module #( A: 1, B: 2 ) ( x: 1, y: _ );
</span>        </span>inst </span>u2: $sv::Module #( A: 1, B: 2 ) ( x: 1, y: _ );
</span>        </span>inst </span>u3: $sv::Module #( A: 1, B: 2 ) ( x: 1, y: _ );
</span>        </span>inst </span>u4: $sv::Module #( A: 1, B: 2 ) ( x: 1, y: _ );
</span>    }
</span>}
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.15.0</a>.</p>


Announcing Verylup 0.1.5
2025-03-24T00:00:00+00:00
The Veryl team has published a new release of Verylup, 0.1.5.
Verylup is the official toolchain installer of Veryl.
It installs the latest Veryl toolchain and eases to update and switch the toolchains.</p>
If you have a previous version of Verylup installed, getting Verylup 0.1.5 is as easy as stopping any programs which may be using Verylup (e.g. closing your IDE) and running:</p>
verylup update
</span></code></pre>
If you don't have it already, please refer Getting Started</a>.</p>
New Features</h1>
Nightly channel</h2>
To use the latest features easily, nightly channel is added.
Nightly channel is built daily from the master branch.</p>
verylup install nightly
</span></code></pre>
By default, nightly channel is not enabled after installation.
So the following ways can be used to enable it.</p>
# Use +nightly
</span>veryl +nightly build
</span>
</span># Set default to nightly
</span>verylup default nightly
</span>
</span># Override by nightly for a specific project
</span>verylup override set nightly
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.1.5</a>.</p>


Announcing Veryl 0.14.1
2025-03-05T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.14.1.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
Resolving Regressions</h1>
This version aims to resolve regressions introduced in the previous version.</p>

Fix broken msb  #1329</a>
</li>
</ul>
New Features</h1>
Improve port connection check #1327</a>
</h2>
Type cast at port connection caused reset type error, it is fixed correctly.</p>
inst </span>u: $sv::SvModule (
</span>    </span>//</span> v0.14.0: `sv_with_implicit_reset` error
</span>    </span>//</span> v0.14.1: no error
</span>    i_rst_n: i_rst </span>as </span>reset_async_low</span>,
</span>);
</span></code></pre>
Connecting unassignable type to output port becomes to be detected.</p>
inst </span>u: Module (
</span>    out0: 1    , </span>//</span> error
</span>    out1: x + 1, </span>//</span> error
</span>);
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.14.1</a>.</p>


Announcing Veryl 0.14.0
2025-03-03T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.14.0.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
Breaking Changes</h1>
New type checker #1216</a>
 #1239</a>
 #1240</a>
 #1264</a>
</h2>
New type checker is introduced to enable the following checks.</p>

Mismatch in array dimensions during assignment</li>
Assigning a 4-state value to a 2-state type</li>
Out-of-range selection for arrays or bits</li>
Interface mismatch during port connection</li>
</ul>
Please see the following blog for the detailed information.</p>
https://veryl-lang.org/blog/new-type-checker/</a></p>
This is not a breaking chage ideally, but the existing code may be broken by mistakes of new checker.
If there is any mistake, please open an issue</a>.</p>
Remove variable declaration from package #1305</a>
</h2>
Variable declaration in package is removed because it is not synthesizable.</p>
package </span>PackageA {
</span>    </span>var </span>X: </span>logic</span>; </span>//</span> Error
</span>}
</span></code></pre>
New Features</h1>
LSP support for file renaming and deleting #1226</a>
</h2>
veryl-ls becomes to support file renaming and deleting to avoid unexpected errors caused by these file operation.</p>
Support clock domain annotation for interface instance #1279</a>
</h2>
Interface instances can have clock domain annotation as the same as normal variables.</p>
var </span>x: </span>`a </span>logic</span>;
</span>
</span>inst </span>intf: </span>`a </span>InterfaceA;
</span></code></pre>
Add align</code> attribute #1283</a>
</h2>
To improve readability of complex expression, align</code> attribute was added.
For example, by adding #[align(number)]</code>, all numbers in expression is aligned.</p>
module </span>ModuleA {
</span>    #[align(number, identifier)]
</span>    </span>let </span>_c : </span>logic</span> = {
</span>        a  [0 ] </span>repeat </span>1 , a  [0 ] </span>repeat </span>1 ,
</span>        aa [1 ] </span>repeat </span>8 , aa [1 ] </span>repeat </span>8 ,
</span>        aaa[2 ] </span>repeat </span>16, aaa[2 ] </span>repeat </span>16,
</span>    };
</span>}
</span></code></pre>
Support default member of modport #1288</a>
</h2>
Default member syntax ..[direction]</code> is introduced to make modport definition concise.
In most cases, the direction of slave-like modport is converse of master-like modport.
So the special direction converse([modport_name])</code> is useful to make clear the definition of master/slave pair.</p>
interface </span>InterfaceA {
</span>    </span>var </span>a: </span>logic</span>;
</span>    </span>var </span>b: </span>logic</span>;
</span>
</span>    </span>modport </span>master {
</span>        a: </span>output</span>,
</span>        b: </span>input</span> ,
</span>    }
</span>
</span>    </span>modport </span>slave {
</span>        ..</span>converse</span>(master)
</span>    }
</span>
</span>    </span>modport </span>monitor {
</span>        ..</span>input
</span>    }
</span></code></pre>
Enable assign</code> to concatenation #1298</a>
</h2>
Concatenation can be used as the left hand side of assign</code> declaration.</p>
assign</span> {a, b} = 1;
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.14.0</a>.</p>


New Type Checker
2025-02-24T00:00:00+00:00
With the new type checker currently under development, it will become possible to perform various type checks that were previously impossible.
As an initial implementation, the following checks are scheduled to be introduced in the next version:</p>

Mismatch in array dimensions during assignment</li>
Assigning a 4-state value to a 2-state type</li>
Out-of-range selection for arrays or bits</li>
Interface mismatch during port connection</li>
</ul>
Furthermore, the Veryl compiler will track parameter overrides across all instances,
including those with recursion, ensuring that it can reliably catch issues that only occur with specific overrides.</p>
For example,</p>
module </span>ModuleX #(
</span>    </span>param </span>A: </span>u32</span> = 1,
</span>) {
</span>    </span>let </span>a : </span>logic</span><2> = 1;
</span>    </span>let </span>_b: </span>logic</span><2> = a[A]; </span>//</span> This bit select causes out-of-range error when A > 2
</span>}
</span>
</span>module </span>ModuleY #(
</span>    </span>param </span>A: </span>u32</span> = 1,
</span>) {
</span>    </span>inst </span>u: ModuleX #(A,);
</span>}
</span>
</span>module </span>ModuleZ {
</span>    </span>inst </span>u: ModuleY #(A: 3,);
</span>}
</span></code></pre>
it will display a warning as follows:</p>
Warning: invalid_select (https://doc.veryl-lang.org/book/07_appendix/02_semantic_error.html#invalid_select)
</span>
</span>  ⚠ invalid select caused by out of range [3:3] > 2
</span>   ╭─[.../test.veryl:5:24]
</span> 4 │     let a : logic<2> = 1;
</span> 5 │     let _b: logic<2> = a[A]; // This bit select causes out-of-range error when A > 2
</span>   ·                        ──┬─
</span>   ·                          ╰── Error location
</span> 6 │ }
</span>   ╰────
</span>    ╭─[.../test.veryl:11:10]
</span> 10 │ ) {
</span> 11 │     inst u: ModuleX #(A,);
</span>    ·          ┬
</span>    ·          ╰── instantiated at
</span> 12 │ }
</span>    ╰────
</span>    ╭─[.../test.veryl:15:10]
</span> 14 │ module ModuleZ {
</span> 15 │     inst u: ModuleY #(A: 3,);
</span>    ·          ┬
</span>    ·          ╰── instantiated at
</span> 16 │ }
</span>    ╰────
</span>  help:
</span></code></pre>
We believe such warnings should ideally be treated as errors.
However, due to the potential for false positives caused by the type checker’s current imperfections,
they will remain warnings until the implementation stabilizes, with plans to upgrade them to errors in the future.</p>
Checks related to bit-width, such as bit-width mismatches during assignment or carry overflow in operations, are ready for implementation.
However, we are still deliberating on the policy regarding which checks should be performed.
Those interested in this issue are encouraged to refer to the Issue page</a>.</p>
The next version, which includes these features, may introduce breaking changes due to significant updates to the checking functionality and is planned to be v0.14.0.
It is scheduled for release within 1-2 weeks, so please look forward to it.</p>


Announcing Veryl 0.13.5
2025-01-31T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.13.5.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
New Features</h1>
Support to override dependencies with local path #1206</a>
</h2>
Sometimes, using dependencies of locally modified version becomes necessary.
In the case, overriding dependencies by local path can be used like below:</p>
[dependencies]
</span>"</span>https://github.com/veryl-lang/sample</span>" </span>= {</span>version </span>= </span>"</span>0.1.0</span>"</span>, </span>path </span>= </span>"</span>../sample</span>"</span>}
</span></code></pre>
This means that if there is ../sample</code>, it is used, and if not, it is pulled from the Git repository.</p>
Introduce inst generic boundary #1192</a>
</h2>
Now instance can be spacified as generics boundary.
The boundary is written like inst X</code>.</p>
module </span>ModuleA {
</span>    </span>function </span>FuncA::<IF: </span>inst </span>InterfaceA> () -> </span>logic</span> {
</span>        </span>return </span>IF.a;
</span>    }
</span>
</span>    </span>inst </span>u: InterfaceA;
</span>    </span>let </span>x: </span>logic</span> = FuncA::<u>();
</span>}
</span>
</span>interface </span>InterfaceA {
</span>    </span>var </span>a: </span>logic</span>;
</span>}
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.13.5</a>.</p>


Announcing Veryl 0.13.4
2025-01-04T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.13.4.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
New Features</h1>
Support port default value #1164</a>
</h2>
Ports of module becomes to be able to have default value.
Ports which have default value can be omitted at the instantiation, and the default values are assigned to the omitted ports.</p>
module </span>ModuleA (
</span>    a: </span>input  logic</span>    ,
</span>    b: </span>input  logic</span> = 1, </span>//</span> default value
</span>    x: </span>output logic</span>    ,
</span>    y: </span>output logic</span> = _, </span>//</span> default value
</span>) {
</span>    </span>assign </span>x = a;
</span>    </span>assign </span>y = b;
</span>}
</span>
</span>module </span>ModubeB {
</span>    </span>inst </span>instA: ModuleA (
</span>        a: 1,
</span>        </span>//</span> b is omitted
</span>        x: _,
</span>        </span>//</span> y is omitted
</span>    );
</span>}
</span></code></pre>
Add mux/demux modules to std library #1148</a>
</h2>
Multiplexer and demultiplexer are added to the standard library.</p>
inst </span>u_mux: $std::mux (
</span>    i_select: _,
</span>    i_data  : _,
</span>    o_data  : _,
</span>);
</span>
</span>inst </span>u_demux: $std::demux (
</span>    i_select: _,
</span>    i_data  : _,
</span>    o_data  : _,
</span>);
</span></code></pre>
Apply ifdef attributes in statement block #1136</a>
</h2>
ifdef</code> attribute can be used in statement block.</p>
always_comb</span> {
</span>    #[ifdef(DEFINE_A)]
</span>    {
</span>        a = 1;
</span>        b = 1;
</span>    }
</span>    #[ifdef(DEFINE_B)]
</span>    c = 1;
</span>}
</span></code></pre>
Support relative path dependency #1099</a>
</h2>
Dependencies to the project through local relative paths can be specified.</p>
[dependencies]
</span>"</span>../../library/path</span>" </span>= </span>"</span>0.1.0</span>"
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.13.4</a>.</p>


Announcing Verylup 0.1.4
2024-12-16T00:00:00+00:00
The Veryl team has published a new release of Verylup, 0.1.4.
Verylup is the official toolchain installer of Veryl.
It installs the latest Veryl toolchain and eases to update and switch the toolchains.</p>
If you have a previous version of Verylup installed, getting Verylup 0.1.4 is as easy as stopping any programs which may be using Verylup (e.g. closing your IDE) and running:</p>
verylup update
</span></code></pre>
If you don't have it already, please refer Getting Started</a>.</p>
New Features</h1>
Add config subcommand</h2>
Now config</code> subcommand is added.
Through the command, you can show the current configuration and change the value.</p>
verylup config show
</span>verylup config set offline true
</span></code></pre>
Show the latest toolchain version</h2>
verylup show</code> shows the latest toolchain version like below:</p>
$ verylup show
</span>installed toolchains
</span>--------------------
</span>
</span>latest: 0.13.3 (default)
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.1.4</a>.</p>


Announcing Veryl 0.13.3
2024-11-25T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.13.3.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
New Features</h1>
Support width cast #1095</a>
</h2>
Bit width cast is added. Now arbitrary expression is not allowed yet as the width, and based</code> and baseless</code> number are only allowed.</p>
assign </span>a = x </span>as </span>2;
</span>assign </span>b = x </span>as </span>10'h2;
</span></code></pre>
Support generic interface with modport #1089</a>
</h2>
Generic interface with modport which means arbitrary interface which has the specified modport are supported.</p>
module </span>ModuleA (
</span>    bus_if: </span>interface</span>::slave,
</span>) {
</span>}
</span></code></pre>
Remove map and doc files by clean</code> command #1061</a>
</h2>
veryl clean</code> command becomes to clean the generated map files and document files.</p>
$ veryl clean
</span></code></pre>
Add pre-defined vector types #1044</a>
</h2>
Some frequent vector types are added to the standard library.
They are combination of 8/16/32/64bit, signed/unsigned and bit/logic.</p>
module </span>ModuleA {
</span>    </span>var </span>a: $std::types::ul8; </span>//</span> 8bit unsigned logic 
</span>    </span>var </span>b: $std::types::il8; </span>//</span> 8bit signed   logic
</span>    </span>var </span>c: $std::types::ub8; </span>//</span> 8bit unsigned bit
</span>    </span>var </span>d: $std::types::ib8; </span>//</span> 8bit signed   bit
</span>}
</span></code></pre>
cond_type</code> attribute #1043</a>
</h2>
To specify unique</code>, unique0</code> and priority</code> in SystemVerilog, cond_type</code> attribute is added.
The attribute can be annotated to case</code> or if</code> statement.</p>

unique</code>: There are no overlapping items. Error if no item matches.</li>
unique0</code>: There are no overlapping items. No error if no item matches.</li>
priority</code>: The first match is used only. Error if no item matches.</li>
</ul>
#[cond_type(unique)]
</span>case </span>a {
</span>
</span>}
</span>
</span>
</span>#[cond_type(priority)]
</span>case </span>a {
</span>}
</span>
</span>#[cond_type(unique0)]
</span>if </span>a {
</span>} </span>else if </span>b {
</span>} </span>else</span> {
</span>}
</span></code></pre>
These attributes enable more aggressive optimization in synthesis, but if the expected condition is not complied, the result of synthesis will be broken.
So these attributes are ignored by default, and if there is the following configuration, Veryl compiler emits them.</p>
[build]
</span>emit_cond_type </span>= </span>true
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.13.3</a>.</p>


Announcing Veryl 0.13.2
2024-10-30T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.13.2.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
New Features</h1>
Allow type as expression #1016</a>
</h2>
Arbitrary type including built-in types becomes to be able to be used in expression context.
For example, logic<10></code> type can be passed as parameter override.</p>
module </span>ModuleA {
</span>    </span>inst </span>x: ModuleB #(
</span>        X: </span>logic</span><10>
</span>    );
</span>}
</span>
</span>module </span>ModuleB #(
</span>    </span>param </span>X: </span>type</span> = </span>logic</span>,
</span>) {}
</span></code></pre>
Shell completion</h2>
Now shell completion for veryl</code> command is supported through verylup</code> installer.
The supported shells are below:</p>

Bash</li>
Elvish</li>
Fish</li>
PowerShell</li>
Zsh</li>
</ul>
If you have already installed verylup</code>, a completion for zsh can be generated by the following command.</p>
verylup completion zsh veryl
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.13.2</a>.</p>


Announcing Veryl 0.13.1
2024-10-11T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.13.1.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
New Features</h1>
This version doesn't contain new features.</p>
Other Changes</h1>
Check out everything that changed in Release v0.13.1</a>.</p>


Announcing Verylup 0.1.3
2024-10-11T00:00:00+00:00
The Veryl team has published a new release of Verylup, 0.1.3.
Verylup is the official toolchain installer of Veryl.
It installs the latest Veryl toolchain and eases to update and switch the toolchains.</p>
If you have a previous version of Verylup installed, getting Verylup 0.1.3 is as easy as stopping any programs which may be using Verylup (e.g. closing your IDE) and running:</p>
verylup update
</span></code></pre>
If you don't have it already, please refer Getting Started</a>.</p>
New Features</h1>
Offline installation support</h2>
Verylup 0.1.3 supports offline installation for environments without internet access.
The procedure of offline installation is below:</p>

Download the latest toolchain package from Veryl release page</a>.</li>
Execute veryl setup</code> with --pkg</code> specification like the following command.</li>
</ul>
verylup setup --offline --pkg veryl-x86_64-linux.zip
</span></code></pre>
If you want to update/install toolchain, --pkg</code> specification is required as the same as setup.</p>
Other Changes</h1>
Check out everything that changed in Release v0.1.3</a>.</p>


Announcing Verylup 0.1.2
2024-09-18T00:00:00+00:00
The Veryl team has published a new release of Verylup, 0.1.2.
Verylup is the official toolchain installer of Veryl.
It installs the latest Veryl toolchain and eases to update and switch the toolchains.</p>
There are two installation ways. In either case, executing verylup setup</code> is required after installing.</p>
Download binary</h2>
Download from release page</a>, and extract to the directory in PATH</code>.</p>
Cargo</h2>
You can install with cargo</a>.</p>
cargo install verylup
</span></code></pre>
New Features</h1>
Self update support</h2>
Verylup 0.1.2 supports self binary updating.
When verylup update</code> is executed, both toolchain update and self update is done.</p>
verylup update
</span></code></pre>
Configuable default toolchain</h2>
If you want to change the default toolchain to a specific toolchain, verylup default</code> can be used.</p>
# set 0.11.0 as default toolchain
</span>verylup default 0.11.0
</span></code></pre>
Additionally, overriding default toolchain per directory is supported too.
You can do verylup override set</code> in your Veryl project.</p>
# set 0.9.0 as default toolchain for the current project
</span>verylup override set 0.9.0
</span></code></pre>
Shell completion</h2>
Shell completion script can be generated by verylup completion</code>.
The supported shells are below:</p>

Bash</li>
Elvish</li>
Fish</li>
PowerShell</li>
Zsh</li>
</ul>
For example, the following command generates a completion script of Verylup for zsh.</p>
verylup completion zsh verylup
</span></code></pre>
After Veryl 0.13.1 (which is not released yet), a completion script of veryl will be supported too like below:</p>
verylup completion zsh veryl
</span></code></pre>
About the usage of generated scripts, please refer the documentation of each shell.</p>
Other Changes</h1>
Check out everything that changed in Release v0.1.2</a>.</p>


Announcing Veryl 0.13.0
2024-09-12T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.13.0.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
If you have a previous version of Veryl installed via verylup</code>, you can get the latest version with:</p>
$ verylup update
</span></code></pre>
If you don't have it already, you can get verylup</code> from release page</a>.</p>
Breaking Changes</h1>
Bounded generic parameter #917</a>
</h2>
Until Veryl 0.13.0, generic parameter couldn't have any restriction.
So Veryl compiler couldn't judge whether the passed parameter is correct at the instantiation,
and it generated the complicated error message.</p>
module </span>ModuleA {
</span>    </span>inst </span>u: GenericModule::<X </span>/*</span> X is OK??? */</span>> (
</span>    };
</span>}
</span></code></pre>
Veryl 0.13.0 adds the following bounds to generic parameter.</p>

const</code></li>
type</code></li>
module prototype</li>
</ul>
const</code> means a constant value, type</code> means any type. The example const</code> and type</code> is below:</p>
//</span> Generic module with const generic parameter
</span>module </span>ModuleA::<X: </span>const</span>> {
</span>}
</span>
</span>//</span> Generic module with type generic parameter
</span>module </span>ModuleB::<X: </span>type</span>> {
</span>}
</span></code></pre>
Module prototype is more complicated, it shows what a module for the generic parameter should has as parameters and ports.
The following ProtoA</code> shows a module should have A</code> and i_clk</code>, and ModuleA</code> satisfies the restriction.
So ModuleA</code> can be used as generic parameter of ModuleB</code> which is bounded by ProtoA</code>.</p>
//</span> Module prorotype
</span>proto </span>ProtoA #(
</span>    </span>param </span>A: </span>u32</span> = 1,
</span>) (
</span>    i_clk: </span>input clock</span>,
</span>);
</span>
</span>//</span> ModuleA satisfies ProtoA
</span>module </span>ModuleA </span>for </span>ProtoA #(
</span>    </span>param </span>A: </span>u32</span> = 1,
</span>) (
</span>    i_clk: </span>input clock</span>,
</span>) {
</span>}
</span>
</span>//</span> Generic module with module prototype
</span>module </span>ModuleB::<X: ProtoA> {
</span>}
</span>
</span>module </span>ModuleC {
</span>    </span>//</span> ModuleA can be used as the generic parameter
</span>    </span>inst </span>u: ModuleB::<ModuleA>;
</span>}
</span></code></pre>
Change from std</code> to $std</code> #930</a>
</h2>
Veryl 0.13.0 change the namespace of standard library from std</code> to $std</code>.
This is because it clears that it is built-in namespace, and reduces conflict with general identifiers.</p>
Change local</code> to const</code> #932</a>
</h2>
local</code> keyword is derived from localparam</code> of SystemVerilog.
The naming is confusable becasue local</code> looks "local scoped" and actually local</code> of package can be seen globally.
So Veryl 0.13.0 changes local</code> to const</code> because const</code> is used for this usage in general programming languages.</p>
module</span> #(
</span>    </span>param </span>X: </span>u32</span> = 1    ,
</span>    </span>const </span>Y: </span>u32</span> = X + 1,
</span>) {
</span>    </span>const </span>Z: </span>u32</span> = 1;
</span>}
</span></code></pre>
New Features</h1>
Support untyped enum declaration #902</a>
</h2>
If the type is omitted in enum declaration, Veryl compiler inserts appropriate type automatically.</p>
enum </span>A {
</span>  FOO,
</span>  BAR,
</span>  BAZ,
</span>}
</span>
</span>//</span> This is equivalence with the above code
</span>enum </span>A: </span>logic</span><2> {
</span>  FOO,
</span>  BAR,
</span>  BAZ,
</span>}
</span></code></pre>
Mermaid support for documentation comment #904</a>
</h2>
Mermaid</a> is syntax to write diagrams.
If ```mermaid</code> is used in documentation comment, the code block is interpreted as Mermaid,
and the generated diagram is shown in documentation.</p>
//</span>/ ```mermaid
</span>//</span>/ graph TD;
</span>//</span>/     A-->B;
</span>//</span>/     A-->C;
</span>//</span>/     B-->D;
</span>//</span>/     C-->D;
</span>//</span>/ ```
</span></code></pre>
Add enum_encoding</code> attribute #915</a>
</h2>
Encoding of variant values in enum can be specified through enum_encoding</code> attribute.
The available encodings are sequential</code>, onehot</code> and gray</code>.</p>
#[enum_encoding(sequential)]
</span>enum </span>A {
</span>  FOO,
</span>  BAR,
</span>}
</span>
</span>#[enum_encoding(onehot)]
</span>enum </span>B {
</span>  FOO,
</span>  BAR,
</span>}
</span>
</span>#[enum_encoding(gray)]
</span>enum </span>C {
</span>  FOO,
</span>  BAR,
</span>}
</span></code></pre>
Completion of modport and struct member #934</a>
</h2>
veryl-ls</code> supports completion of modport and struct member.</p>
struct </span>A {
</span>    x: </span>logic</span>,
</span>    y: </span>logic</span>,
</span>}
</span>
</span>var </span>a: A;
</span>let </span>b: </span>logic</span> = a.
</span>//</span>              | `x` and `y` will be listed as completion candidates at inputting this period
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.13.0</a>.</p>


verylup: Veryl toolchain installer
2024-09-05T00:00:00+00:00
verylup is the official toolchain installer of Veryl.
It installs the latest Veryl toolchain and eases to update and switch the toolchains.</p>
Installation</h1>
There are two installation ways. In either case, executing verylup setup</code> is required after installing.</p>
Download binary</h2>
Download from release page</a>, and extract to the directory in PATH</code>.</p>
Cargo</h2>
You can install with cargo</a>.</p>
cargo install verylup
</span></code></pre>
Usage</h1>
verylup</code> can be used like below:</p>
// Setup verylup (only once at first)
</span>verylup setup
</span>
</span>// Update the latest toolchain
</span>verylup update
</span>
</span>// Install a specific toolchain
</span>verylup install 0.12.0
</span>
</span>// Show installed toolchains
</span>verylup show
</span></code></pre>
After installing verylup</code>, verion specifier by +</code> can be used in veryl</code> command like below:</p>
// Use the latest toolchain
</span>veryl build
</span>
</span>// Use a specific toolchain
</span>veryl +0.12.0 build
</span>veryl +latest build
</span></code></pre>
For Veryl Developer</h1>
For Veryl developer, a special toolchain target local</code> is prepared.
If verylup install local</code> is executed in your local Veryl repository, the built toolchain is installed as local</code> toolchain.
local</code> becomes the default toolchain if it exists.</p>
// Build and install the toolchain from local Veryl repository
</span>verylup install local
</span>
</span>// Use the built toolchain
</span>veryl build
</span>
</span>// Use the latest toolchain
</span>veryl +latest build
</span></code></pre>


Announcing Veryl 0.12.0
2024-08-21T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.12.0.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
The latest version of Veryl can be downloaded from release page</a>.</p>
Breaking Changes</h1>
Forbid continuous casting #887</a>
</h2>
Until Veryl 0.12.0, casting by as</code> could be continuous, but it is forbidden by Veryl 0.12.0.
If continuous casting is required, it can be achieved by inserting ()</code>.</p>
//</span> Syntax error
</span>assign </span>a = x </span>as </span>u32 </span>as </span>i32</span>;
</span>//</span> OK
</span>assign </span>a = (x </span>as </span>u32</span>) </span>as </span>i32</span>;
</span></code></pre>
Change symbol of clock domain annotation #883</a>
</h2>
Until Veryl 0.12.0, clock domain annotation used single quotation mark like 'x</code>.
Veryl 0.12.0 changes it to backtick mark like `x</code>.</p>
//</span> Syntax error
</span>var </span>a: 'x </span>clock</span>;
</span>//</span> OK
</span>var </span>a: </span>`x </span>clock</span>;
</span></code></pre>
New Features</h1>
Expand inside</code> operation #873</a>
</h2>
Some EDA tools doesn't support inside</code> operation.
For these tools, expand_inside_operation</code> configuration of Veryl.toml</code> can be used like below:</p>
[build]
</span>expand_inside_operation </span>= </span>true
</span></code></pre>
If the configuration is enabled, inside</code> operations in the generated SystemVerilog are expanded like below:</p>

Default</li>
</ul>
assign </span>a = ((1 + 2 / 3) </span>inside</span> {0, 0..10, 1..=10});
</span></code></pre>

Expand</li>
</ul>
assign </span>a = ((1 + 2 / 3) ==? 0) ||
</span>           ((1 + 2 / 3) >= 0 && (1 + 2 / 3) < 10) ||
</span>           ((1 + 2 / 3) >= 0 && (1 + 2 / 3) <= 10);
</span></code></pre>
Waveform dump support through veryl test --wave</code> #898</a>
</h2>
Waveform dump in integrated test is supported.
If --wave</code> option is specified at veryl test</code>, [test name].vcd</code> files are generated.
The generation place is the same as generated SystemVerilog code by default.
It can be configured through waveform_target</code> in Veryl.toml</code>.</p>
[test]
</span>waveform_target </span>= {</span>type </span>= </span>"</span>directory</span>"</span>, </span>path </span>= </span>"</span>[dst dir]</span>"</span>}
</span></code></pre>
Cocotb support for integrated test #899</a>
</h2>
As the way of embed</code> and language specifier, cocotb</code> and py</code> are supported now.
If cocotb</code> is specified, the embeded code are interpreted as cocotb code and executed through external Python3 environment.
cocotb requires to specify the name of top module, so it should be specified through the second argument of #[test]</code> attribute.</p>
To use this feature, python3</code> environment in which cocotb</code> 1.9.0 is installed is required.</p>
#[test(test1, ModuleA)]
</span>embed</span> (cocotb) py{{{
</span>import </span>cocotb
</span>
</span>@cocotb.test()
</span>async def test(dut):
</span>    dut.i_d.value = 0
</span>}}}
</span>
</span></code></pre>
Embed standard library into compiler #878</a>
</h2>
Standard library is embeded into Veryl compiler, and it can be used through std</code> namespace.
For example, std::fifo</code> is FIFO module in standard library, and can be used without adding dependency like below.
All list and documentation is https://std.veryl-lang.org</a>.</p>
module </span>ModuleA {
</span>    </span>inst </span>u: std::fifo (
</span>        i_clk        : _,
</span>        i_rst        : _,
</span>        i_clear      : _,
</span>        o_empty      : _,
</span>        o_almost_full: _,
</span>        o_full       : _,
</span>        o_word_count : _,
</span>        i_push       : _,
</span>        i_data       : _,
</span>        i_pop        : _,
</span>        o_data       : _,
</span>    );
</span>}
</span></code></pre>
The public API of standard library is not stable until Veryl 1.0.
If there is any idea or suggestion, please open issue or pull request at https://github.com/veryl-lang/std</a>.</p>
Other Changes</h1>
Check out everything that changed in Release v0.12.0</a>.</p>


Announcing Veryl 0.11.3
2024-08-09T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.11.3.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
The latest version of Veryl can be downloaded from release page</a>.</p>
New Features</h1>
Improve naming lint #858</a>
 #870</a>
</h2>
Some missing rules of naming lint was added.
They are suffix rules and rules for function argument.</p>
[lint.naming]
</span>suffix_enum </span>= </span>"</span>_enum</span>"
</span></code></pre>
Check missing clock domain #864</a>
</h2>
If there are some clocks in a module, clock domain annotation became mandatory.
The following code causes missing_clock_domain</code> error.</p>
module </span>ModuleA (
</span>    clk0: </span>input clock</span>, </span>//</span> should be `clk0: input 'a clock`
</span>    clk1: </span>input clock</span>, </span>//</span> should be `clk1: input 'b clock`
</span>) {
</span>}
</span></code></pre>
If the two clocks belong the same clock domain, implicit clock domain can be specified like below:</p>
module </span>ModuleA (
</span>    clk0: </span>input</span> '_ </span>clock</span>,
</span>    clk1: </span>input</span> '_ </span>clock</span>,
</span>) {
</span>}
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.11.3</a>.</p>


Announcing Veryl 0.11.2
2024-08-06T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.11.2.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
The latest version of Veryl can be downloaded from release page</a>.</p>
New Features</h1>
This version doesn't contain new features.</p>
Other Changes</h1>
Check out everything that changed in Release v0.11.2</a>.</p>


Announcing Veryl 0.11.1
2024-07-03T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.11.1.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
The latest version of Veryl can be downloaded from release page</a>.</p>
New Features</h1>
Add sourcemap-resolver to release build #810</a>
</h2>
sourcemap-resolver</code> binary was added to release package.
It can be used as filter program throught pipe like below:</p>
$ make | sourcemap-resolver
</span></code></pre>
By sourcemap-resolver</code>, file location in log can be resolved to the location in Veryl.</p>

Before pipe</li>
</ul>
%Error: /path/test.sv:23:1: syntax error, unexpected endmodule
</span>   23 | endmodule
</span>      | ^~~~~~~~~
</span></code></pre>

After pipe</li>
</ul>
%Error: /path/test.sv:23:1: syntax error, unexpected endmodule
</span>        ^ from: /path/test.veryl:18:18
</span>   23 | endmodule
</span>      | ^~~~~~~~~
</span></code></pre>
Add raw identifier #806</a>
</h2>
Some Veryl's keyword can be used as identifier in SystemVerilog.
So instantiating a SystemVerilog module may cause syntax error.</p>
module </span>ModuleA (
</span>    i_clk: </span>input clock</span>,
</span>    i_rst: </span>input reset</span>,
</span>) {
</span>    </span>inst </span>u0: $sv::ModuleSV (
</span>        </span>clock</span>: i_clk, </span>//</span>syntax error because `clock` is Veryl's keyword
</span>        </span>reset</span>: i_rst, </span>//</span>syntax error because `reset` is Veryl's keyword
</span>    );
</span>}
</span></code></pre>
To fix it, raw identifier was introduced.
It starts with r#</code> prefix and transpiled into an identifier without the prefix.</p>
module </span>ModuleA (
</span>    i_clk: </span>input clock</span>,
</span>    i_rst: </span>input reset</span>,
</span>) {
</span>    </span>inst </span>u0: $sv::ModuleSV (
</span>        r#</span>clock</span>: i_clk, </span>//</span> transpiled into `.clock(i_clk),`
</span>        r#</span>reset</span>: i_rst, </span>//</span> transpiled into `.reset(i_rst),`
</span>    );
</span>}
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.11.1</a>.</p>


Announcing Veryl 0.11.0
2024-06-24T00:00:00+00:00
The Veryl team has published a new release of Veryl, 0.11.0.
Veryl is a new hardware description language as an alternate to SystemVerilog.</p>
The latest version of Veryl can be downloaded from release page</a>.</p>
Breaking Changes</h1>
Clock domain annotation support #789</a>
</h2>
If there are some clocks in a module, clock domain annotation is required.
Clock domain annotation represents which clock domain each port belongs to.
Additionally, assignment over different clock domains requires unsafe (cdc)</code> block.</p>
module </span>ModuleA (
</span>    </span>//</span> clock domain 'a
</span>    i_clk_a: </span>input</span>  'a </span>clock</span>,
</span>    i_dat_a: </span>input</span>  'a </span>logic</span>,
</span>    o_dat_a: </span>output</span> 'a </span>logic</span>,
</span>
</span>    </span>//</span> clock domain 'b
</span>    i_clk_b: </span>input</span>  'b </span>clock</span>,
</span>    i_dat_b: </span>input</span>  'b </span>logic</span>,
</span>    o_dat_b: </span>output</span> 'b </span>logic</span>,
</span>) {
</span>    </span>unsafe</span> (cdc) {
</span>        </span>//</span> assignment from 'a domain to 'b domain
</span>        </span>assign </span>o_dat_b = i_dat_a;
</span>    }
</span>}
</span></code></pre>
New Features</h1>
Support importing functions into modport #742</a>
</h2>
Function in interface can be imported through import</code> direction in modport</code> declaration.</p>
interface </span>InterfaceA {
</span>    </span>var </span>a: </span>logic</span>;
</span>
</span>    </span>function </span>get_a () -> </span>logic</span> {
</span>        </span>return </span>a;
</span>    }
</span>
</span>    </span>modport </span>slave {
</span>        a    : </span>input</span> ,
</span>        get_a: </span>import</span>,
</span>    }
</span>}
</span></code></pre>
Add signed literal support #770</a>
</h2>
Signed literal with s</code> prefix is supported.</p>
module </span>ModuleA {
</span>    local a: </span>u32</span> = 32'sb1111;
</span>    local b: </span>u32</span> = 32'so7777;
</span>    local c: </span>u32</span> = 32'sd9999;
</span>    local d: </span>u32</span> = 32'shffff;
</span>}
</span></code></pre>
Enhance case statement/expression #783</a>
</h2>
As case item, range expression and expression with constant value can be used.
switch</code> which has arbitrary expression as the condition items is added too.</p>
module </span>Module16 {
</span>    local P: </span>bit</span> = 1;
</span>
</span>    </span>var </span>a: </span>logic</span>;
</span>    </span>var </span>b: </span>logic</span>;
</span>    </span>let </span>x: </span>logic</span> = 1;
</span>    </span>let </span>y: </span>logic</span> = 1;
</span>
</span>    </span>always_comb</span> {
</span>        </span>case </span>x {
</span>            5..=7  : a = 1;
</span>            P - 1  : a = 1;
</span>            </span>//</span> Error because y is not constant value
</span>            </span>//</span>y - 1  : a = 1;
</span>            </span>default</span>: a = 1;
</span>        }
</span>    }
</span>
</span>    </span>always_comb</span> {
</span>        </span>switch</span> {
</span>            </span>//</span> arbitrary expression includuing variable can be used
</span>            y == 0 : b = 1;
</span>            </span>default</span>: b = 1;
</span>        }
</span>    }
</span>}
</span></code></pre>
Other Changes</h1>
Check out everything that changed in Release v0.11.0</a>.</p>

Veryl

Announcing Veryl 0.20.1

New Tool Features</h1>

Veryl Simulator: Performance Comparison with Verilator

What's next</h2> The simulator is still under active development. We plan to extend the benchmark to other CPU architectures and a wider range of designs, and to publish the benchmark setup so the numbers can be reproduced.</p>

Announcing Veryl 0.20.0

New Language Features</h1>

New Tool Features</h1>

Announcing Veryl 0.19.1

New Tool Features</h1>

Announcing Veryl 0.19.0

New Language Features</h1>

New Standard Library</h1>

Announcing Veryl 0.18.0

New Language Features</h1>

New Tool Features</h1>

Announcing Verylup 0.1.12

Semantic Analysis based on Intermediate Representation

Refering before definition</h3> In the following code, a</code> is referred before it's definition.</p>

Announcing Veryl 0.17.2

Announcing Veryl 0.17.1

New Standard Library</h1>

Announcing Verylup 0.1.11

Custom CA bundle support for downloads</h2> In environments behind a proxy that re-signs HTTPS traffic with an enterprise root CA, custom CA bundle support is necessary. verylup becomes to load a custom CA bundle through SSL_CERT_FILE</code> environment variable or OS-dependent CA stores.</p>

Announcing Verylup 0.1.10

New Features</h1> VersionReq syntax support</h2> VersionReq syntax like +0.16</code> instead of complete version +0.16.0</code> can be used. If +0.16</code> is specified, the latest version in 0.16.x</code> is selected.</p>

VersionReq syntax support</h2> VersionReq syntax like +0.16</code> instead of complete version +0.16.0</code> can be used. If +0.16</code> is specified, the latest version in 0.16.x</code> is selected.</p>

aarch64-windows support</h2> aarch64-windows</code> platform support is added.</p>

Announcing Veryl 0.17.0

New Tool Features</h1>

Information</h1> DOI of Veryl release</h2> After this version, DOI (Digital Object Identifier) is added to all Veryl release. If you refer Veryl in your paper, please use the following DOI.</p>

DOI of Veryl release</h2> After this version, DOI (Digital Object Identifier) is added to all Veryl release. If you refer Veryl in your paper, please use the following DOI.</p>

Update the Visual Studio Code extension

Announcing Veryl 0.16.5

Official Docker image

Additional Maintainer

Announcing Verylup 0.1.9

New Features</h1>

Announcing Veryl 0.16.4

New Tool Features</h1>

GitLab supports syntax highlighting of Veryl

Announcing Veryl 0.16.3

New Tool Features</h1>

Announcing Verylup 0.1.7

Announcing Veryl 0.16.2

New Tool Features</h1>

Announcing Verylup 0.1.6

New Features</h1> Add proxy support</h2> Verylup supports HTTP/SOCKS5 proxy. By default, verylup refers system proxy configuration via the following environment variables:</p>

Add proxy support</h2> Verylup supports HTTP/SOCKS5 proxy. By default, verylup refers system proxy configuration via the following environment variables:</p>

Add aarch64-linux support</h2> Now verylup supports aarch64-linux. The supported platforms are below:</p>

Other Changes</h1> Check out everything that changed in Release v0.1.6</a>.</p>

What's next</h2>
The simulator is still under active development. We plan to extend the benchmark to other CPU architectures and a wider range of designs, and to publish the benchmark setup so the numbers can be reproduced.</p>

Custom CA bundle support for downloads</h2>
In environments behind a proxy that re-signs HTTPS traffic with an enterprise root CA, custom CA bundle support is necessary. verylup becomes to load a custom CA bundle through `SSL_CERT_FILE</code> environment variable or OS-dependent CA stores.</p>`

aarch64-windows support</h2>
`aarch64-windows</code> platform support is added.</p>`

Add aarch64-linux support</h2>
Now verylup supports aarch64-linux. The supported platforms are below:</p>

x86_64-linux</li>
x86_64-mac</li>
x86_64-windows</li>
aarch64-linux</li>
aarch64-mac</li> </ul>
Other Changes</h1>
Check out everything that changed in Release v0.1.6</a>.</p>

Other Changes</h1>
Check out everything that changed in Release v0.1.6</a>.</p>