The Veryl team has published a new release of Veryl, 0.13.2. Veryl is a new hardware description language as an alternate to SystemVerilog.

If you have a previous version of Veryl installed via verylup, you can get the latest version with:

$ verylup update

If you don't have it already, you can get verylup from release page.

New Features

Allow type as expression #1016

Arbitrary type including built-in types becomes to be able to be used in expression context. For example, logic<10> type can be passed as parameter override.

module ModuleA {
    inst x: ModuleB #(
        X: logic<10>
    );
}

module ModuleB #(
    param X: type = logic,
) {}

Shell completion

Now shell completion for veryl command is supported through verylup installer. The supported shells are below:

• Bash
• Elvish
• Fish
• PowerShell
• Zsh

If you have already installed verylup, a completion for zsh can be generated by the following command.

verylup completion zsh veryl

Other Changes

Check out everything that changed in Release v0.13.2.