The Veryl team has published a new release of Veryl, 0.16.0. Veryl is a new hardware description language as an alternate to SystemVerilog.

If you have a previous version of Veryl installed via verylup, you can get the latest version with:

$ verylup update

If you don't have it already, you can get verylup from release page.

Breaking Changes

To migrate some syntax changes, veryl migrate can be used:

// Check how changes will be applied
$ veryl migrate --check

// Migrate
$ veryl migrate

Keep directory hierarchy for target = {type = "directory"} #1513

target = {type = "directory"} caused to break files which have the same name and belong different source directory, because it forces all output files to a single directory. To avoid this issue, the behaviour of this option is changed to keep directory hierarchy of source.

Change clock domain annotation symbol to ' #1517

Clock domain annotation symbol was ` by parser restriction. But it is changed to ' as the same as Rust's lifetime annotation by improving parser implementation.

// Before
i_clk: input `a clock,

// After
i_clk: input 'a clock,

Unsupport enum / struct / union declarations in interface declaration #1521

enum, struct and union in interface declaration were removed because they can't be refered from the outside of the interface. If you use them, please move them to a package.

Typed generic boundary #1548

const as generic boundary was removed, and typed generic boundary is introduced. This is because const can't express a boundary for enum. veryl migrate converts all const to u32 boundary.

// Before
package PkgA::<X: const, Y: const> {}

// After
package PkgA::<X: u32, Y: EnumX> {}

Forbid last item with ifdef in comma-separated list #1572

The last item with ifdef in comma-separated list becomes to be forbidden. This is because adjusting last comma by complex ifdef combination is difficult.

module ModuleA (
    a: input logic,
    #[ifdef(B)] // this `ifdef` is forbidden
    b: input logic,
) {}

Forbid project name starting with __ #1580

A project name starting with __ becomes to be forbidden, because it is used for Veryl compiler internally.

$ veryl new __a
Error:   × project name "__a" is reserved by system

New Language Features

elsif / else attribute #1453

elsif and else attribute can be used with ifdef or ifndef.

always_comb {
    #[ifdef(DEFINE_A)]
    a = 1;
    #[elsif(DEFINE_B)]
    b = 1;
    #[else]
    c = 1;
}

Proto alias declaration #1473

alias can be used in proto declaration.

proto package ProtoPackageA {
    alias module InstModule: ProtoModuleA;
}
package PackageA::<M: ProtoModuleA> for ProtoPackageA {
    alias module InstModule = M;
}

Modport expansion #1512

Some synthesis tools don't support modport as ports of the top module or boundary of hiererchical synthesis. For such cases, if #[expand(modport)] is specified, Veryl compiler expands modport of the module.

#[expand(modport)]
module ModuleA (
    slv_if: modport InterfaceA::slave ,
    mst_if: modport InterfaceA::master,
) {}

Skip to write files if no change #1518

If the existing generated files have the same contents which Veryl compiler is trying to emit, writing files is skipped. By this change, the compatibility with timestamp based tools like GNU make is improved.

Default project structure #1531

As the default project structure, veryl new will create the following file and directories.

.gitignore
Veryl.toml
src/
target/

Interface prototype #1532

Interface prototype becomes to be supported like below:

proto interface InterfaceA {
  function FuncA(a: input logic, b: input logic) -> logic;

  modport mp {
    FuncA: import,
  }
}

u8, u16, i8 and i16 fixed types #1537

u8, u16, i8 and i16 become to be supported as primitive types.

let a: u8  = 0;
let a: u16 = 0;
let a: i8  = 0;
let a: i16 = 0;

Use modport as function argument #1554

Now modport can be used as function argument. Veryl compiler expands these modport to separated variables.

function FunctionA (
    slv_if: modport InterfaceA::slave ,
    mst_if: modport InterfaceA::master,
) {}

AXI3, AXI4, AXI4-Lite interfaces and prototypes in Veryl standard library #1577

Generic AXI3, AXI4, AXI4-Lite interfaces are added in Veryl standard library.

alias package axi3_pkg = $std::axi3_pkg::<32, 4, 8>;

module ModuleA (
    slv_if: modport $std::axi3_if::<axi3_pkg>::slave,
) {}

Other Changes

Check out everything that changed in Release v0.16.0.