The Veryl team has published a new release of Veryl, 0.18.0. Veryl is a new hardware description language as an alternate to SystemVerilog.

If you have a previous version of Veryl installed via verylup, you can get the latest version with:

$ verylup update

If you don't have it already, you can get verylup from release page.

Breaking Changes

To migrate some syntax changes, veryl migrate can be used:

// Check how changes will be applied
$ veryl migrate --check

// Migrate
$ veryl migrate

Allow concatenation assignment in always, and add block keyword #2175

Bit concatenation in left-hand side of always_comb and always_ff is allowed now.

always_comb {
    {a, b} = 1;
}

On the other hand, this feature conflicts the existing statement grouping syntax by {}. So new block keyword is introduced to avoid the conflicts.

always_comb {
    // grouping by `{}` is not allowed
    //{
    //    a = 1;
    //    b = 1;
    //}

    block {
        a = 1;
        b = 1;
    }
}

Split bool type to bbool and lbool types #2186

Using bool in const context caused assigning 4-state variable to 2-state variable because bool is type alias of logic<1>.

const flag: bool = true;
const X: u32 = if flag ? 10 : 20; // 4-state variable is used in const context

To avoid this mismatch, bbool and lbool is introduced instead of bool.

• bbool: the type alias of bit<1>
• lbool: the type alias of logic<1>

const flag: bbool = true;
const X: u32 = if flag ? 10 : 20;

New Language Features

#[allow(unassign_variable)] attribute #2147

By IR-based semantic analyzer, unassign check was enhanced. If you want to disable the check, #[allow(unassign_variable)] attribute can be used.

#[allow(unassign_variable)]
module Module A {
}

New Tool Features

Introduce IR-based semantic analyzer #2005

The new IR-based semantic analyzer is introduced. Please refer the following post for the detailed changes.

Semantic Analysis based on Intermediate Representation

Other Changes

Check out everything that changed in Release v0.18.0.